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Graphenedielectric integration for graphene transistors
Lei Liao a, Xiangfeng Duan a,b,*aDepartment of Chemistry & Biochemisty, University of California, Los Angeles, CA 90095, USAbCalifornia Nanosystems Institute, University of California, Los Angeles, CA 90095, USA
Contents
1. Introduction: the promise and challenges for graphene electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
1.1. The promise of graphene electronics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
1.2. Graphene dielectric integration and its impact on transistor performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
2. Physical vapor deposition of top-gate dielectrics on graphene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
2.1. Raman characterization of graphenedielectric integration by PVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
2.2. Top-gated graphene transistors using PVD dielectrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
3. Atomic layer deposition of top-gate dielectrics on graphene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
3.1. Challenges in direct ALD of top-gate dielectrics on graphene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
3.2. Molecular buffer layer for ALD deposition of oxide dielectrics on graphene. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
3.3. Metal oxide buffer layer for ALD of dielectrics on graphene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
3.4. Low-k polymer buffer layer for ALD of dielectrics on graphene. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
4. Physical assembly of high-k oxide nanostructures as top-gate dielectrics for graphene transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
4.1. Dielectric properties of Al2O3 nanoribbons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3624.2. Dielectric nanostructuregraphene integration and interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
4.3. Al2O3 nanoribbons as the top-gate dielectrics for graphene transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
4.4. ZrO2 nanowire as top-gate dielectric for graphene nanoribbon transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
4.5. Conductor/dielectric coreshell nanowires as the top-gate for graphene nanoribbon transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
4.6. Integrated device array from nanowire gated graphene nanoribbon transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
5. Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Materials Science and Engineering R 70 (2010) 354370
A R T I C L E I N F O
Article history:
Available online 8 August 2010
Keywords:
Semiconductor
Graphene
Transistor
Dielectrics
Nanowires
Nanoribbons
A B S T R A C T
Graphene is emerging as an interesting electronicmaterial for future electronics due to its exceptionally
high carrier mobility and single-atomic thickness. Graphenedielectric integration is of critical
importance for the development of graphene transistors and a new generation of graphene based
electronics. Deposition of dielectric materials onto graphene is of significant challenge due to the
intrinsic material incompatibility between pristine graphene and dielectric oxide materials. Here we
review various strategies being researched for graphenedielectric integration. Physical vapor
deposition (PVD) can be used to directly deposit dielectric materials on graphene, but often introduces
significant defects into the monolayer of carbon lattice; atomic layer deposition (ALD) process has also
been explored to deposit high-k dielectrics on graphene, which however requires functionalization ofgraphene surface with reactive groups, inevitably leading to a significant degradation in carrier
mobilities. Using naturally oxidized thin aluminum or polymer as buffer layer for dielectric deposition
can mitigate the damages to graphene lattice and improve the carrier mobility of the resulted top-gated
transistors. Lastly, a physical assembly approach has recently been explored to integrate dielectric
nanostructures with graphene without introducing any appreciable defects, and enabled top-gated
graphene transistors with the highest carrier mobility reported to date. We will conclude with a brief
summary and perspective on future opportunities.
2010 Elsevier B.V. All rights reserved.
* Corresponding author at: Department of Chemistry & Biochemistry, and California Nanosystems Institute, University of California, Los Angeles, CA 90095, USA.
E-mail address: [email protected] (X. Duan).
Contents lists available at ScienceDirect
Materials Science and Engineering R
j o u r n a l h o m e p a g e : w w w . e l s e v i e r . c o m / l o c a t e / m s e r
0927-796X/$ see front matter 2010 Elsevier B.V. All rights reserved.
doi:10.1016/j.mser.2010.07.003
http://dx.doi.org/10.1016/j.mser.2010.07.003mailto:[email protected]://www.sciencedirect.com/science/journal/0927796Xhttp://dx.doi.org/10.1016/j.mser.2010.07.003http://dx.doi.org/10.1016/j.mser.2010.07.003http://www.sciencedirect.com/science/journal/0927796Xmailto:[email protected]://dx.doi.org/10.1016/j.mser.2010.07.003 -
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1. Introduction: the promise and challenges for graphene
electronics
1.1. The promise of graphene electronics
Graphene is a one-atom-thickplanar sheet of sp2-bondedcarbon
atoms arranged in a honeycomb crystal lattice (Fig. 1a and b) [1,2].
Graphene has attracted considerable interest in the past several
years due to its significant potential for both the fundamental
studies and technological applications [321]. Graphene is charac-
terizedby a linear dispersion relation withthe Dirac point separating
the valence and conduction bands witha zerobandgap, which limits
the achievable onoff current ratios but does not rule out analogue
radio frequency (RF) device applications. In particular, it has been
demonstrated that graphene exhibits the highest carrier mobilities
exceeding 200,000 cm2/V s [11], which is not only $100 timesgreater than that of silicon but also about 10 times better than the
state-of-the-art high mobility semiconductors lattice-matched to
indium phosphide. Along with many other desirable properties,
including large critical current densities ($2 108 A/cm2) [22], ahigh saturation velocity (5.5 107 cm/s) [23], and a micrometer-scale mean free path at room temperature, graphene is currently
regarded as a highly promising materials for high-speed electronics
[2328]. These desirable properties promise graphene to offerexcellent short-circuit current-gain cutoff frequency (fT) for high
frequency applications. In particular, it has been recently demon-
strated that high speed graphene devices were achieved with a
cutoff frequency fT reaching up to 100 GHz, demonstrating the
significant potential of graphene devices for radio frequency (RF)
applications (Fig. 1c and d) [25].
Dueto thezero-band-gap nature, bulk graphene remains highly
conductive even at the charge neutrality point, and therefore
cannot be used for effective field-effect transistors (FETs) at room
temperature for digital applications. The formation of graphene
nanostructures with lateral quantum confinement can open up a
finite band gap to enable room temperature FET operation ( Fig. 2)
[10,2937]. It has been demonstrated that sub-10 nm graphene
nanoribbons (GNRs) can be created, and used to fabricate FETs that
can be effectively switched off at room temperature [31,32]. We
have recently developed a rational approach to fabricate GNRs
with controllable widths from 6 to 20 nm using chemical
synthesized nanowires as the physical etch masks [35]. Impor-
tantly, using such GNR as the semiconducting channel, we have
fabricated room temperature FETs with onoff ratios> 100
(Fig. 2a). It has also been demonstrated that graphene nanomesh,
as a mimick of graphene nanoribbon networks, can effectively
introduce a finite conduction band gap into the two-dimensional
graphene to enable room temperature transistors with comparable
on/off ratios (Fig. 2b) [34].
1.2. Graphene dielectric integration and its impact on transistor
performance
The gate dielectric is an essential component of a transistor.Compared to the semiconductor channel, the gate dielectrics have
received much less attention due to the relative uninteresting
nature of an insulator, despite its significant impact on the critical
device parameters including transconductance, subthreshold
swing and frequency response. Among the various strategies
explored to fabricate graphene or graphene nanostructure based
Fig. 1. Graphene as a potential electronic material. (a) Schematic illustration of graphene as an atomic-scale honeycomb lattice of carbon atoms. (b) TEM image of graphene,
adapted from [2]. (c) Image of radio frequency devices fabricated on a 2-inch graphene wafer and schematic cross-sectional view of a top-gated graphene FET. (d) Measured
small-signal currentgain jh21j as a function of frequency f fora 240-nm-gateand a 550-nm-gate graphene FETat VD = 2.5 V. Cutofffrequencies,fT, were53 and 100 GHzforthe
550 and 240-nm devices, respectively. Adapted from [25].
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FETs, most efforts employ a silicon substrate as a global back gate
and a 300 nm thick silicon dioxide (SiO2) as the gate dielectrics.
This substrate is used primarily because the graphene can be
readily visualized using optical microscope on this particular
substrate due to optical interference [3842]. The readily viewable
graphene on the 300 nm SiO2 substrate has allowed easy devicefabrication and led to many interesting scientific discoveries. The
requirement of 300 nm SiO2, however, can intrinsically limit the
resulted device performance in several perspectives. First, optical
detection technique to visualize graphene has been demonstrated
and widely used for a SiO2 thickness of 300 nm, but a 5% variation
in thickness (e.g. to 315 nm) can significantly lower the contrast
[40]. Second, the devices made on 300 nm SiO2 substrate have
small gate capacitance due to the relatively large dielectric
thickness and the small dielectric constant, and thus require high
switching voltage [43].
Exploring high-k dielectric substrate may mitigate these
problems [43,44]. For example, we have demonstrated that a
72 nm Al2O3/Si substrate is superior to the 300 nm SiO2/Si
substrate for both the visualization of graphene and the transistorperformance [43]. Compared to the 300 nm SiO2/Si substrate, the
72 nm Al2O3/Si substrate can enhance the optical contrast of single
layer graphene by at least 3 times. Furthermore, using the Al2O3film as the gate dielectrics, the back-gated graphene FETs have
been fabricated to exhibit more than 7-fold increase in transcon-
ductance.
It is important to note that the carrier mobility of the resulting
graphene transistors can be significantlyimpactedby the nature of
the dielectric layer and graphenedielectric interface. Theoretical
studies suggest that the intrinsic mobility of graphene, set by
longitudinal acoustic (LA) phonon scattering, can reach
105 cm2 V1 s1 at room temperature [45]. However, the achiev-
able carrier mobility in an actual device can often be limited by
extrinsic scattering sources, many of which arise from the surfacemorphology, chemistry, structural, and electronic properties of the
substrate. For example, recent calculation suggests that a mobility
as high as 44,000 cm2 V1 s1 can be achievedin graphene on SiO2/
Si substrate at room temperature, which is limited by the phonon
scattering [4548]. Experimental studies have demonstrated that
mobility values in the range of 220 103 cm2 V1 s1 for thegraphene transistor made on SiO2/Si substrate [49]. The variability
in mobility is attributed to various degrees of local disorder in
graphene and in the dielectric substrate.
Increasing the mobility beyond the extrinsic limits is one of the
central challenges of the graphene community. Recently, two
groups have reported a significant improvement in the mobility of
suspended graphene after current-heating annealing [12,50].
However, a more device friendly solution may rely on placing
graphene on a different substrate. Several alternatives have
been explored,however, the mobility obtained so far is comparable
to that on SiO2 [51]. Utilization of high-k dielectric material as
the gate insulator is expected to partially screen charged
impurities and enhance the carrier mobility [48]. A recent report
demonstrates significant carrier mobility improvement to7 104 cm2 V1 s1 in graphene transistors using single-crystalepitaxial PbZr0:2Ti0:8O3 (PZT) films as the gate oxide [44]. This
remarkable improvement was attributed to the strong screening of
PZT film and possible ordered adsorbate molecular layer at
interface that may reduce the scattering [52].
On the other hand, most studies of graphene transistors
discussed above employ a silicon substrate as a global back gate,
which, although useful for fundamental investigations, will be of
limited use for practical applications due to the inability to
independently address multiple devices on the same chip. Top-
gated devices can readily allow independently addressable device
arrays and functional circuits, and therefore are of significant
interest [5355]. The formation of top-gated graphene transistors
requires direct deposition of dielectric oxide material on top ofpristine graphene, which is of significant challenge due to the
intrinsic incompatibility between these two types of materials.
Deposition of oxide dielectrics onto graphene for top-gated
transistors can often introduce substantial defects into graphene
lattice and lead to significant degradation in carrier mobilities
[23,27,5661]. Here we review various strategies, including
physical vapour deposition (PVD), atomic layer deposition (ALD)
and physical assembly approach, for graphenedielectric integra-
tion for top-gated graphene transistors, discussing the potential
merits and challenges of each.
2. Physical vapor deposition of top-gate dielectrics on
graphene
Physical vapour deposition (PVD) such as electron-beam
evaporation or sputtering process is a common approach to
deposit a variety of oxide dielectric thin films on many different
substrates including graphene. However, the PVD process usually
yields lower quality dielectrics and can cause significant damages
to graphene.
2.1. Raman characterization of graphenedielectric integration by
PVD
Raman spectroscopy has been used to study the interaction
between single layer graphene and PVD dielectrics ( Fig. 3) [62].
Various PVD approaches, including electron beam evaporation,
pulsed laser deposition (PLD) and radio frequency (RF) sputter,
Fig. 2. Graphene nanostructures for the opening of a conduction gap in graphene. (a) Schematic view of a graphene nanoribbon (inset) and transfer characteristics of a
grapnene nanoribbon transistor with on/off ratio > 100. (c) Schematic view of a graphene nanomesh (inset) and transfer characteristics of a grapnene nanomesh transistor
with on/off ratio > 100. Adapted from [34] and [35].
L. Liao, X. Duan/ Materials Science and Engineering R 70 (2010) 354370356
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were explored to deposit SiO2 layer on graphene. Raman spectra of
the graphene covered with these PVD SiO2 layers all show largedefect band (D-band), indicating substantial defects introduced
into the graphene lattice. Strong defect-induced D band was also
observed in Raman spectra of graphene covered with PLD
deposited HfO2. In contrast, simple spin coating of polymer
dielectric such as polymethyl methacrylate does not introduce D-
band. These results clearly demonstrate that PVD process can
result in significant damage to carbon lattice, and simple spin
coating would not introduce obvious defects.
2.2. Top-gated graphene transistors using PVD dielectrics
The PVD dielectric film can be used as top-gate dielectrics for
graphene transistors. However, due to the significant damage the
process can cause, the mobility values observed in the top-gateddevices fabricated from this process are typically nearly one order
of magnitude smaller than those achieved in the back-gated
devices. For example, Lemme et al. reported the top-gated
graphene transistors, in which electron-beam evaporated SiO2was used as the top-gate dielectric [58]. Before the deposition of
the top-gate dielectric, the charge carrier mobilities in the
uncovered graphene are estimated to be mh = 4790 cm2 V1 s1
and me = 4780 cm2 V1 s1. In stark contrast, the room tempera-
ture mobility valuesare severely degraded tomh = 710 cm2 V1 s1
and me = 530 cm2 V1 s1 after the deposition of the SiO2 (Fig. 4).
This study highlights that the PVD deposited dielectric layer can
significantly disrupt the charge transport characteristics in
graphene.
3. Atomic layer deposition of top-gate dielectrics on graphene
Atomic layer deposition (ALD) is a well developed approach for
growing high-k gate dielectric layers, owing to its precise control
over the film thickness and uniformity [63]. However, the direct
deposition of high-k dielectric materials, such as Al2O3 and HfO2,
on graphene using H2O-based ALD is not possible because of the
hydrophobic nature of graphene basal plane [64] and the lack of
functional groups for molecular absorption which is necessary for
ALD.
3.1. Challenges in direct ALD of top-gate dielectrics on graphene
The attempt to directly deposit oxide dielectrics on pristine
graphene using ALDfailedto produce continuous layer of dielectrics.
Because a perfect graphite surface is chemically inert [65], attempts
togrowALDAl2O3 layer on a clean highly orientedpyrolyticgraphite
surface leadto onlya selective growth at the steps between graphite
layers, where the broken carbon bonds along the terraces serve as
one-dimensional nucleation center for the initial ALD process [66].
Fig. 5a and b shows AFM images of the same area before and afterALD of $2 nm Al2O3. Before ALD, the height of the triangulargraphene pieceat thebottom and thelargepiece onthe leftwas$1.7and$2.0 nm, respectively.Near the edgeof the graphene, there wasalso a narrow $1.0 nm high stripe. After ALD, $2.0 nm Al2O3 wascoated on SiO2. The apparent topography height of the three
graphene sheets was obviously reduced to a level similar to that of
the ALD-coated SiO2. The height difference before and after ALD
suggests that no Al2O3 was effectively coated on pristine graphene
sheets. This is because ALD relies on chemisorption and rapid
reaction of precursor molecules with surface functional groups
[67,68]. As a result, no ALD canoccur on thepristine grapheneplane
since it does not have any dangling bonds or surface functional
groups to react with the precursors. Interestingly, quasicontinuous
bright lines of Al2O3 preferentially grown on the edges of thegraphene sheets, suggesting dangling bonds or possible termination
by OH or other reactive species on the edges. Some bright dots in
the middle of graphene sheets may correspond to ALD Al2O3 island
around the defects such as pentagonhexagon pairs or vacancies
known to exist in graphite [69].
The unsuccessful ALD attempts to deposit oxide dielectrics on
graphene call for additional surface functionalization to create
functional groups for oxide nucleation. The key idea enabling the
high-k dielectric layer growth on graphene by ALD is to provide
intentional nucleation sites on the inert surface of graphene. To
this end, Lin et al. has used a functionalization layer consisting of
Fig. 3. Raman spectra of the graphene show a clear defect band emerging at
1350 cm1 after PVD dielectric deposition using various approaches, suggesting
significant defects are introduced into graphene lattice during the dielectric
deposition process. Adapted from [62].
Fig. 4. (a)SEM image of a graphene transistor with PVDtop-gate dielectrics. (b)Back-gatetransfer characteristics of graphene-FETwith andwithout a topgate. Adapted from
[58].
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50cyclesof NO2-TMA (trimethylaluminum)in ALD process prior to
the growth of gate oxide. This NO2-TMA functionalization layer
was essential for the ALD process and allowed us to achieve a
uniform thin (
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$2 nmAl2O3. Before ALD,the height of the graphene under the linecut was $1.6 nm, which increased to $3.0 nm after ALD. Therelative height increase of Al2O3-coated graphene was partly
attributed to the thickness of PTCA layer, which was usually $0.50.8 nm observed by AFM after PTCA coating step. The actual Al2O3on graphene was $2.8 0.2 nm thick in Fig. 7c. AFM images showcontinuous coverage of dielectric layer on the entire graphene area
with a root of mean square roughness of the Al2O3 film on graphene
about 0.33 nm, suggesting uniform packing of the underlayer PTCA
molecules. Previous high vacuum STM studies have confirmed two
modes of epitaxial packing of the PTCA precursor, perylene
tetracarboxic dianhydride, along the lattice lines of highly oriented
pyrolytic graphite [75,76]. As thepartitioning of PTCA from methanol
to the graphene interface is highly favorable, it is likely that similar
epitaxial packing is occurring in the solution phase, yielding dense,
uniform coating on graphene. This self-assembled PTCA layer on
graphene is responsible for uniform Al2O3 film coating. The non-
covalent functionalization method is not destructive to graphene
lattices andmay be used fordepositing ultrathinhigh-k dielectrics for
future graphene electronics [27].
3.3. Metal oxide buffer layer for ALD of dielectrics on graphene
An alternative buffer layer is oxidized metal thin film. In this
approach, a very thin layer of metal film is first deposited on
graphene and allowed to oxidize to form a thin oxide layer, which
can function as the nucleation layer for subsequent oxide
deposition by ALD. For example, Kim et al. introduced a thin
nucleation layer of oxidized aluminum between the graphene
layer and the Al2O3 dielectric [77]. Prior to the Al2O3 layer growth
by ALD, a 12 nm thick aluminum layer was deposited on thegraphene surface by e-beam evaporation. This aluminum nucle-
ation layer was completely oxidized as soon as the sample was
exposed in air before transferring into ALD chamber [78,79]. The
samples were transferred to the ALDchamber for the deposition of
Al2O3 using trimethylaluminum as the aluminum source and H2O
as the oxidizer. Initial stage of ALD growth starts with an H2O
oxidizing cycle at elevated temperatures to ensure the complete
oxidation of aluminum.
Top-gated graphene transistors have been fabricated to test the
dielectric quality and its impact on the graphene devices. To
fabricate the device, nickel thin film as the source and drain
electrodes were first defined using electron beam lithography on
mechanically peeled graphene, followed by an annealing step in a
hydrogen atmosphere at 200 8C to remove possible contaminantssuch as resist residues [80]. Al nucleation layer was then deposited
by high vacuum e-beam evaporator. The sample was then exposed
in air and transferred into the ALD chamber and went through 167
cycles of Al2O3 deposition, resulting in a 15 nm thick Al2O3 film. A
50 nm thick nickel top-gate electrode was subsequently fabricated
to obtain the final device (Fig. 8a and b).
Fig. 7. ALD ofAl2O3 on PTCA-coated graphene. (a) Schematic illustration of perylene
tetracarboxylic acid (PTCA)-coated graphene. PTCA selectively adheres to graphene
on SiO2 surfaces, providing binding sites for TMA deposition. Inset is a top view of
PTCA structure. (b) AFM image of graphene on SiO2 before ALD. The height of the
triangular shaped graphene is $1.6 nm as shown in the height profile along thedashed line cut. Scale bar is 500 nm. (c) AFM image of the same area as (a) after
$2 nm Al2O3 ALD deposition. The height of the triangular shaped graphenebecomes $3.0 nmas shownin the heightprofilealong the dashed linecut.Scale baris500 nm. (dand e)Schematicsof graphene onSiO2 beforeand after ALD.The Al2O3grows uniformly on non-covalently PTCA-coated graphene. Adapted from [73].
Fig. 8. Dual gate graphene transistors with Al2O3 top-gate dielectric deposited using thin aluminum as buffer layer. (a) Schematic of dual-gated graphene FET structure. (b)
Opticalmicroscope image of a graphene FET. (c) Rtot vs. VTG data measured at different VBG values.The inset shows theposition ofVDirac,TG at different VBG. Optical microscope
image of a graphene FET. Adapted from [77].
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The electrical transport characterizations were conducted at
room temperature in a vacuum probe station. The top-gate
electrode and the silicon substrate were used as a local gate and
global back-gate, respectively, to control the carrier concentration
and polarity in the graphene layer. Fig. 8c shows the total device
resistance (Rtot) as a function of top-gate voltage measured at
different back-gate biases from 40 to 40 V and a drain bias ofVD = 0.1 V. At VBG = 0 V, the sample resistance reaches a maximum
(Dirac point) at VDirac,TG = 0.08 V. This observation indicates that
there was little unintentional doping of the graphene sample after
the top-gate stack deposition. As jVTGVDirac,TGj increases, theelectron or hole concentration in the graphene channel increases
and Rtot decreases, resulting in V-shaped traces. Importantly, the
top-gated device shows a very small hysteresis less than 0.05 V,
and low leakage current less than 0.75 pA/mm2 through the Al2O3dielectric, highlighting a high dielectric quality and a low interface
state density.
The Rtot vs. VTG measured at different VBG values shows an
applied VBG bias changes the position of the Dirac point and also
shifts vertically the measured resistance values (Fig. 8c). The
change in the Dirac point position can be explained as follows: a
positive (negative) VBG bias induces a finite concentration of
electrons (holes) in the active area, which is proportional to the
back-gate capacitance (CBG). In order to restore the device to theDirac point, where the carrier concentration is minimum, a
negative (positive) applied VTG is required. The vertical shift is
caused by the resistance change in the un-top-gated regions of the
graphene flake. The shift of the top-gate Dirac points as a function
of VBG can be used to determine top-gate and back-gate
capacitances, CTG/CBG$ 28 (inset of Fig. 8c). Using the back-gatecapacitance value ofCBG = 11 nF/cm
2, the top-gate capacitance can
be estimated to be CTG = 306 nF/cm2, corresponding to a relative
dielectric constant of 6.0 for the Al2O3 film.
To determine the impact of the dielectric deposition, it is
important to determine the carrier mobility. To accurately derive
the mobility value, the contact resistance should be carefully
excluded as it is comparable to the graphene transistor channel
resistance. The authors have adopted a model to exclude theimpact of the contact resistance as detailed below. The carrier
concentrations (electrons or holes) in the graphene channel
regions ntot can be approximated by
ntot ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
n20 nVTG2q
(1)
where n0 represents residual carrier concentration at Dirac point,
which should be zero for an ideal, disorder-free graphene layer and
none zero in presence of charged impurities located either in the
dielectric or at the graphene/dielectric interface [81]. nVTGrepresents the carrier concentration induced by the top-gate bias
away from the Dirac point, VTG VTG VTG;Dirac. The expression fornVTG is obtained from thefollowing equation relating VTG, Cox, andthe quantum capacitance of the two-dimensional electrons in the
graphene channel:
VTG VTG;Dirac e
Cn hvF
ffiffiffiffiffiffiffipn
pe
(2)
The total device resistance Rtot is given by
Rtot Rcontact Rchannel Rcontact L=W
nem
Rcontact L=Wffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffin20 nVTG2em
q (3)
where Rchannel is the resistance of the graphene channel coveredby top-gate electrode, the contact resistance Rcontact consists of
the uncovered graphene section resistance and the metal/
graphene contact resistance, and L and W represent the channel
length and width the top-gated area [23]. By fitting this model
to the measured data, the authors extracted a phenomenal
mobility m of 8600 cm2/Vs, representing the highest value
achieved in top-gated transistors at the time of their report. This
approach to use aluminum nucleation layer for ALD was also
adopted by IBM scientists to fabricate top-gated graphene
devices to achieve field effect mobility about 2700 cm2/V s [24],
a respectable value, although not as high as the first report
(Fig. 9).
The metal oxide as the buffer/nucleation layer has also been
explored for the deposition of oxide on graphene using otherapproach such as molecular beam epitaxy (MBE). Wang et al.
demonstrated that the growth of atomically smooth magnesium
Fig. 9. (a) Device schematic of the dual-gate graphene transistor. (b) SEM image of a double-channel graphene transistor. The channel width is 27 mm, and the gate length is350 nm for each channel. (c) Measured channel conductance as a function of the back-gate voltage of a graphene device before and after the deposition of 12-nm-thick ALD
Al2
O3
. Prior to the ALD process, a layer of 2-nm aluminum is deposited and oxidized as the nucleation layer. Adapted from [24].
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oxide (MgO)films on graphene surfaces by MBE [82]. By examining
AFM images of MgO films with different growth rates on highly
oriented pyrolytic graphite (HOPG) substrates, they found that the
high surface diffusion led to non-uniform MgO films with root
mean square roughness> 0.8 nm. To reducethe mobilityof surface
atoms, they deposit Ti atoms to dress the graphene surface prior to
the MgO deposition. Remarkably, with as little as a 0.5 ML
(monolayer) coverage of Ti, the root mean square roughness of a
1 nm MgO film is dramatically reduced to be near the atomic
spacing in MgO (0.211 nm). Because the metallic Ti islands on
graphene maybe undesirable for lateral transport, they oxidize the
Ti prior to MgO growth and find that the MgO layer is atomically
smooth under this condition as well. However, the mobility of
these devices is still limited, as low as 8001700 cm2/V s.
The use of a thin metal (Al or Ti) film as a nucleation layer has
enabled the ALD of continuous oxide dielectric (e.g. Al2O3) on
graphene. The device results show mobility values of several
thousand at room temperature, an encouraging finding that
indicates that the top-gate stack does not severely increase the
carrier scattering and consequently degrade the device character-
istics.
3.4. Low-k polymer buffer layer for ALD of dielectrics on graphene
Farmer et al. reported that the introduction of a low-k polymer
buffer layer for ALD of high-k dielectrics on graphene, and
demonstrated top-gated devices without significant mobility
degradation [14]. The low-k bufferlayer consists of a commercially
available polymer NFC 1400-3CP, which is a derivative of
polyhydroxystyrene that is conventionally used as a planarizing
underlayer in lithographic processes. It can be diluted in propylene
glycol monomethyl ether acetate (PGMEA), and spin-coated onto
the graphene surface. The dilution and spin speed can be adjusted
to control the desired thickness and uniformity of the buffer layer.
Methyl and hydroxyl groups contained within the polymer
structure serve as functional groups for ALD of HfO2 using
tetrakis(dimethylamido)-hafnium and water as the precursors.
In a typical process, approximately 10 nm thick polymer bufferlayer was first spin coated and cured at 175 8C for 5 min to remove
residual solvent, and 10 nm thick HfO2 is deposited onto the buffer
layer to complete the dielectric stack. The ALD was conducted at a
relatively low temperature of 125 8C to produce HfO2 films with a
dielectric constant ofk = 13. Capacitance analysis of the complete
gate stack yields a dielectric constant ofk = 2.4 for the buffer layer.
The impact of the buffer dielectric processing on the transport
properties of the back-gated graphene devices was examined by
comparing two-point transfer characteristics (Fig. 10b) and
transconductances (inset of Fig. 10b) at different stages of the
processing. The two-point transconductance is defined asgm = dID/
dVG, where ID is the drain current and VG is the gate voltage. The
Dirac point voltage (VDirac) of the device before processing is
VDirac = 3.5 V, in close proximity to 0 V, which signifies that thegraphene is not significantly doped by the supporting 300 nm SiO2substrate. The doping level became highly p-doped after applica-
tion of the buffer layer (VDirac = 42.5 V), and then moderately p-
doped after HfO2 ALD (VDirac = 13.25 V). After ALD, the device was
subjected to an O2 plasma treatment which further shift the device
towards neutral doping (VDirac = 5.75 V), but did not damage the
graphene as indicated by relatively little change in resistance or
transconductance. This also demonstrates that the dielectric stack
caneffectivelyprotect graphene from damaging by theplasma that
is known to etch graphene. Beyond changing the doping level,
buffered dielectric processing has a minimal effect on the transfer
characteristics. Both the minimum current value at VDirac and the
maximum hole transconductance remain within 15% of theirinitial
values. There is a 40% decrease in the maximum electron
transconductance, which is likely associated with doping-induced
conductance asymmetry caused by the electrodes [83,84]. The
mobility values achieved here is 8500 cm2/V s for back gated
configuration (with top-gate dielectrics) and 7600 cm2/V s for top-gated configuration. Overall, the results obtained here show a
significant improvement compared to other methods of dielectric
coating (Fig. 10a). Indeed, the authors have demonstrated in
parallel experiments that devices made with the polymer buffer
layer are significantly better than those made with other
approaches, such as NO2 functionalization and oxidized Al
deposition discussed before.
The addition of a low-k polymer buffer layer between
graphene and conventional gate dielectrics helps minimize
mobility degradation in top-gated graphene transistors. Possible
reasons include the suppression of extrinsic surface phonons by
the buffer layer and the reduction of the impurity concentration
due to the inherent properties of the polymer. This new coating
procedure represents a significant improvement over previousefforts, and will hopefully further the advancement of graphene
transistors.
4. Physical assembly of high-k oxide nanostructures as top-
gate dielectrics for graphene transistors
Despite significant efforts devoted to the functionalization of
graphene surface or introduction of buffer layer for ALD of oxide
Fig. 10. Two-point back-gated measurements of graphene flakes. (a) Transfer characteristics and corresponding transconductances (inset) after the different stages of
buffered dielectric processing: beforeprocessing (gray), afterNFC polymer deposition (green),after HfO2 deposition(blue), andafter50 W O2 plasmatreatments for30 s (red)
. Theschematicshowsthe completeddevice configuration. (b)Transfer characteristics of twodevices before (solidlines)and after (dashedlines) alternative coating processes
areemployed.Two nanometers oxidized Al deposition (red) and NO2 functionalization (blue) is usedinstead of polymer coating. Both processes result in significant mobility
degradation. VD = 10 mV forall measurements,and VBG is swept forwardand backwardto showcurrent hysteresis(For interpretation of thereferences to colour in this figure
legend, the reader is referred to the web version of the article.). Adapted from [14].
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dielectrics on graphene, and significant advancements in this
direction, these processes usually break the chemical bonds or
introduce undesired impurities in the graphene lattice, inevitably
leading to a significant degradation in deviceperformance. Many of
these processes can result in mobility degradation by nearly one
order of magnitude. The use of aluminum buffer layer for high-k
deposition was demonstrated with improved device mobility,
which, however, is still lower than that of normal back-gated
graphene devices [4,45,49,85,86]. Introduction of a polymer buffer
layer prior to high-k deposition can mitigate the potential damage
to graphene lattice, which however can limit the effective gate
coupling due to the low-k polymer layer. To eventually realize
high-performance graphene-based electronics, continued effort is
necessary to develop alternative approaches that can enable
graphenedielectric integration without damaging the pristine
graphene lattice. To this end, we have recently reported an entirely
new strategy to integrate graphene with high-k dielectrics by
physical assembling free-standing oxide nanowires or nanorib-
bons on top of graphene [8789]. Here we review the recent
advancements in this regard.
Nanowires and nanoribbons can be synthesized at high
temperature with nearly perfect crystalline structure, but manip-
ulated and assembled at room temperature. This flexibility allows
the integration of normally incompatible materials and processesand can enable unique new functions in electronics or photonics
[53,9093]. Physical assembly of freestanding dielectric nanos-
tructures on graphene represents the mildest approach for
graphenedielectric integration. Specifically, high quality dielec-
tric nanostructures were first synthesized, and then transferred
onto graphene as the gate dielectrics for top-gated graphene
transistors. This integration approach preserves the pristine nature
of the graphene and allows us to achieve the highest room
temperature carrier mobility in top-gated graphene transistors to
date. Fig. 11 illustrates our approach to fabricate top-gated
graphene transistors using oxide nanostructures as the gate
dielectrics. Oxide dielectric nanostructures (e.g. nanoribbons)
were first aligned on top of the graphene through a physical dry
transfer process, followed by lithography and metallizationprocess to define the source and drain electrodes (Fig. 11a).
Oxygen plasma etch was then used to remove the exposed
graphene, leaving only the graphene protected underneath the
dielectric nanostructure and the source drain electrodes (Fig. 11b).
The top gate electrode was then fabricated to obtain a functional
transistor (Fig. 11c).
4.1. Dielectric properties of Al2O3 nanoribbons
Aluminum oxide (Al2O3) nanoribbons were used as an initial
example to demonstrate the concept of using free-standing
chemical nanostructures as the top-gate dielectrics for graphene
transistors [89], due to their excellent dielectric properties,
thermal and chemical stability [94]. Al2O3 nanoribbons were
synthesized through a physical vapour transport approach at
1200 8C [95]. Transmission electron microscope (TEM) studies
showthattheAl2O3 nanoribbonstypically have a width of 13mm,and a length on the order of 10 mm (Fig. 12a). Selected areaelectron diffraction (SAED) shows the nanoribbon has a single
crystallinea-Al2O3 structure, oriented along h1 1 0i direction in itslong axis, and along h0 0 1i direction (c-plane) in its thickness(inset of Fig. 12a). The high resolution TEM image (HRTEM)
confirms that the nanoribbon is a single crystal with nearly perfect
crystalline structure free of any obvious defects (Fig. 12b). Atomic
force microscopy (AFM) studies show the nanoribbons typically
have a thickness around 15150 nm (Fig. 12c), and nearly
atomically smooth surface with root mean square roughness less
than 0.2 nm (Fig. 13d).
The intrinsic dielectric properties (current tunnelling, break-
down and dielectric constant) of the Al2O3 nanoribbons were
characterized using a metalinsulatormetal (MIM) device
(Fig. 12e). Currentvoltage (IV) measurements of the MIM device
show typical FowlerNordheim (FN) tunnelling behaviour with a
breakdown field of$8.5 MV/cm (Fig. 12f and inset), comparable tothe best quality ALD Al2O3 film [94]. This type of field assisted
tunnelling can be described by charge carrier tunnelling through a
triangular barrier with:
J AE2OXexpBEOX
(4)
where
A 1:54 106 1mFB
(5)
and
B 6:83 107m1=2FB3=2 (6)
Jis current density, EOX is the oxide electric field, m* is the effective
mass of the charge carrier, which is about 0.23me, and FB is the
barrier height [94]. Fitting the IV characteristics with FN
tunnelling model gives a tunnel barrier of about 2.0 eV betweenAl2O3 and Ti, comparable to previous reports of the barrier height
between ALD Al2O3 and metals of similar work function [94,96].
The relative dielectric constant is also determined as 8.5 from
capacitancevoltage measurement, which is larger than typical
values observed in ALD Al2O3 films. These studies clearly
demonstrate that the Al2O3 nanoribbons have dielectric properties
comparable to or better than the best quality ALD Al2O3 film, and
can function as an excellent dielectric material for top-gated
graphene transistors.
4.2. Dielectric nanostructuregraphene integration and interface
The Al2O3 nanoribbons can be aligned onto the top of the
graphene through a solution assembly or physical transfer process.
Fig.11. Schematic illustration of thefabrication processto obtain top-gated graphenetransistors using dielectricoxidenanostructures(e.g.nanoribbons) as theetching mask
and top-gate dielectric. (a) A dielectric nanostructure is aligned on top of graphene using a dry-transfer process without any additional chemical functionalization to
minimize the possibility to introduce defects/impurities into the graphenedielectric interface, and the sourcedrain electrodes are fabricated by electron-beamlithography.
(b) Oxygen plasma etch is used to remove the unprotected graphene, leaving only the graphene underneath the dielectric nanostructure connected to two large graphene
blocks underneath the source and drain electrodes. (c) The top gate electrode is defined through lithography and metallization process. Adapted from [89].
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Previous studies have shown that the deposition of oxide on top of
graphene often introduced significant defects into the graphene
structure with an obvious defect band (D-band) emerging around
1350 cm1 in Raman spectra [62]. To this end, micro-Raman
spectroscopy was employed to investigate the interaction between
an Al2O3 nanoribbon and the underlying graphene (Fig. 13a).
Micro-Raman spectra were collected from bare graphene (point a)
and Al2O3 nanoribbon covered graphene (point b). Significantly,
there is no clear difference between two Raman spectra and there
is no obvious D-band (Fig. 13b), in contrast to previous study in
which an obvious D-band was observed[109]. Cross-sectionalTEM
was used to study the graphenedielectric interface (Fig. 13c). The
image of the device shows that the graphene layers are intimately
integrated with the crystalline Al2O3 nanoribbon without any
obvious gap or impurities between them (Fig. 13d). Together, these
studies clearly demonstrate that the physical assembly approach
can effectively integrate Al2O3 nanoribbon with graphene without
introducing any appreciable defects into the graphene lattice, and
thus can effectively preserve the high carrier mobility in the
resulting devices.
4.3. Al2O3 nanoribbons as the top-gate dielectrics for graphene
transistors
The electrical transport studies of the top-gated graphene
transistors using Al2O3 nanoribbon gate dielectrics were carried
Fig. 12. Evaluation of the Al2O3 nanoribbons as dielectric material. (a) TEM image (inset, SAED pattern) and (b) HRTEM image of an Al2O3 nanoribbon show nearly perfect
crystalline structure with a-Al2O3 structure. (c) AFM image of an Al2O3 nanoribbon with thickness $50 nm. The image area is 5 mm 5 mm. (d) AFM image of the surface ofthe Al2O3 nanoribbon, highlighting the smooth surface with a root mean square roughness < 0.2 nm. The image area is 250 nm 250 nm. (e)The schematic device diagram(inset) and SEM image of an Al2O3 nanoribbon metalinsulatormetal (MIM) device. (f) Current densityelectric field (JE) curve of an MIM device made from an Al2O3nanoribbon, and the inset shows the corresponding FowlerNordheim (FN) curve. Adapted from [89].
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out at room temperature. Fig. 14a shows the drainsource current
(Ids) vs. drainsource voltage (Vds) output characteristics of the
transistor at various top-gate voltages (VTG). The device delivers an
on-current of 675mA at Vds = 1 V and Vg =
1.5 V. Importantly, the
transfer characteristics (Ids vs. top-gated voltage (VTG) and back-gated voltage (VBG)) show the required gate voltage swing to
achieve similar current modulation in top-gate configuration is
more than one order of magnitude smaller than that in back-gate
configuration (Fig. 14b and inset). The transconductance gm = dIds/
dVTG can be extractedfrom the IdsVTG curve (Fig. 14c). At Vds = 1 V,
the top-gated device exhibits a max gm of about 290mS, which isabout 15 times larger than that of the back-gated configuration
(gm $ 19.5mS).Fig. 15a further shows two-dimensional plot of the device
conductance as a function of varying VBG and VTG bias, from which
we can determine the top-gate Dirac point (VTG_Dirac) shift as a
function of VBG (Fig. 15b). It gives the ratio between top-gate and
back-gate capacitances, CTG/CBG% 14.3. This gate capacitance ratio
is consistent with the improvement factor ($15) in transconduc-tance of top- vs. back-gated configurations. Using the back-gate
capacitance value ofCBG = 11.5 nF/cm2, the top-gate capacitance is
estimated to be CTG = 164.5 nF/cm2, corresponding to a relative
dielectric constant of 8.4 for Al2O3 nanoribbon, which is alsoconsistent with the value obtained from MIM devices.
The same model described above [Section 3.3] was used to fit
the measured data and extract the relevant parameters, n0, Rcontactand m. Fig. 15c shows the measured Rtot vs. VTG (black line), along
with thefitted curve derived from Eq. (3) (red line).The fitted curve
agrees well with the experimental data, with a single value of the
residual concentration n0 = 4.1 1011 cm2, Rcontact = 1240V, andthe mobility m = 22,400 cm2/V s, which represents the highest
carrier mobility value observed in top-gated graphene devices to
date. Multiple devices were fabricated and tested with the same
approach, all of which exhibited carrier mobilities well exceeding
10,000 cm2/V s with highest mobility of reach 23,600 cm2/V s,
comparable to the best reported values in back-gated devices and
Fig.13. Characterization of the graphene/Al2O3 nanoribbon interface.(a) An optical image of an Al2O3 nanoribbon on graphene, thescalebar is 2mm. (b)Ramanspectra of thegraphene with (b) and without (a) Al2O3 nanoribbon covering. There is no D-band in either spectrum, indicating that Al2O3 nanoribbon does not introduce any appreciable
defects into graphene lattice. (c) A cross-section TEM image of the top gate stack, the scale bar is 100 nm. The inset shows an SEM image of a typical device, the scale bar
indicates 5mm. The dotted line in the inset shows the cross-section cutting direction. (d) A cross-section HRTEM image of the interface between Al2O3 nanoribbon and a tri-layer graphene. The partially incomplete graphene layers in the image are caused by electron beam damage during the TEM imaging process. Adapted from [89].
Fig. 14. Room temperature electrical properties of thetop-gatedgraphene deviceusing Al2O3 nanoribbon as thegate dielectric. (a) IdsVds outputcharacteristics, the channel
width and length ofthe deviceis 2.1 and 4.1 mm (b)Transfer characteristics at Vds = 1 V forthe deviceusing topand backgate(inset). (c)Transconductancegm asa functionoftop-gate voltage V
TG, the inset shows the g
mvs. V
BG. The plots indicate the top-gate g
mis about 15 times higher than the back-gate g
m. Adapted from [89].
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significantly better than typical values previously reported for top-
gated devices (Fig. 16). Together, these studies clearly demonstrate
that the presence of Al2O3 nanoribbon on top of graphene does not
lead to any mobility degradation, in contrast to previous efforts in
using ALD or PVD to deposit dielectrics on graphene.
4.4. ZrO2 nanowire as top-gate dielectric for graphene nanoribbon
transistors
Taking a step further, ZrO2 nanowires with even higher
dielectric constant (up to 23) [97,98] were also explored as the
gate dielectric for top-gated graphene devices [88]. An additional
attribute of using ZrO2 nanowires is that narrower graphene
channels (e.g. graphene nanoribbons, GNR) can be readily
fabricated to facilitate gap-opening and improve the transistor
onoff ratio [3033,35,99]. ZrO2 nanowires were synthesized
through a chemical vapour deposition (CVD) process using ZrCl4 as
the precursor. Scanning electron microscope (SEM) image shows
that ZrO2 nanowires are about several tens of microns in length
and 20100 nm in diameter (Fig. 17a). TEM and SAED studies
reveal that ZrO2 nanowires are amorphous (Fig. 17b and inset). The
top-gated graphene transistors using ZrO2 nanowires as the gate
dielectric can be fabricated using the same approach describedabove (Fig. 17c). Here the ZrO2 nanowire also functions as a
nanoscale etch mask to define a narrow graphene nanoribbon with
width in the 1020 nm regime through aggressive over etch (inset,
Fig. 17c) [35]. The IdsVds plots at various top-gate voltages (VTG)
show clearly that the device conductance decreases as the gate
potential increases towards positive direction (Fig. 17d), demon-
strating that the graphene nanoribbon is p-type doped, which can
be attributed to edge oxidation or the physisorbed O2 from
ambient or during the device fabrication process. This device
delivers an on-current of 28mA at Vds = 1 V and Vg = 1.0 V.Transfer characteristics show a top-gated GNR transistor using
ZrO2 nanowire dielectric can be switched on andoff with only $1 Vof gate swing (red curve in Fig. 17e), in contrast to 1040 V
required for back-gated devices (black curve in Fig. 17e). The
device shows a room temperature on/off ratio of$12at Vds = 0.1 V,consistent with a graphene nanoribbon with estimated width of
$1015 nm [30,35]. The maximum transconductance gm atVds = 1 V is about 29 mS, more than 12 times larger than that ofthe back-gated configuration ($2.3mS) (Fig. 17f).
It is interesting to compare the top-gated graphene nanoribbon
devices with state-of-the-art silicon MOSFETs. The effective on
current Ion for an FET device is usually characterized at Vds = Vg(on
off) = Vdd, where Vg(onoff) is the gate voltage swing from off- to on-
state and Vdd is the power supply voltage. Considering Vds = Vg(on
off) = Vdd = 1 V, the Ion of our device at Vds = 1 and 1 V gate swing
from the off state is $25mA. Taking the channel width of thegraphene nanoribbons $ 15 nm, we obtain the scaled values of Ionand gm of our device to be
$1.7 mAmm1 and
$2.0 mSmm1,
already exceeding the values of 0.7 mA mm
1 and 0.8 mS mm
1 insub-100-nm silicon p-MOSFETs and comparable to those of n-
MOSFET devices employing high-k dielectrics [100]. This is
significant considering the relatively large channel length
($1mm) of the current device. It is reasonable to expect thatthe on-current and transconductance can be further improved by
shrinking the channel length. These studies demonstrate that ZrO2
Fig.15. Mobility determinationin thetop-gated graphene deviceusingAl2O3 nanoribbon as thegate dielectric.(a) Two-dimensional plot of thedevice conductanceat varying
VBG and VTG bias.Theunitin thecolor scale ismS. (b)The top-gate Dirac point VTG_Dirac at different VBG. (c)Experimentalplot (blackline) andmodellingfitting (redline)ofRtotvs. VTGVTG_Dirac relation to derive the contact resistance and carrier mobility (For interpretation of the references to colour in this figure legend, the reader is referred to the
web version of the article.). Adapted from [89].
Fig. 16. Table summarizing the highest mobility values obtained in top-gated graphene transistors using various dielectric integration approaches.
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nanowires can also function as effective gate dielectrics for high
performance top-gated graphene nanoribbon devices.
4.5. Conductor/dielectric coreshell nanowires as the top-gate for
graphene nanoribbon transistors
In the above discussions, pure dielectric nanostructures wereexplored as the top-gate dielectric for graphene transistors, in
which the dielectric thickness was controlled by the overall
dimensionof thenanostructuresand may be difficult to scale down
to very small thickness (e.g. 12 nm), due to the challenges in
synthesizing and assembling the oxide nanostructures at such
small dimensions, and the potential difficulties in fabricating
devices with such small structures. Alternatively, one can also
explore conductor/dielectric coreshell nanostructures (nanowires
or nanoribbons), in which the dielectrics are deposited on a
conducting (e.g. metal or highly doped semiconductor) nanos-
tructure using ALD, and can be precisely controlled down to 1 nm
regime. Such coreshell nanowires can be used to fabricate top-
gated graphene transistors using a similar approach described
above, in which the oxide shell functions as the gate dielectricswith controlled thickness, andthe conducting core functionsas the
self-integrated gate. Using such coreshell nanostructures, it is
possible to fabricate top-gated graphene transistors with the
dielectric thickness down to 1 nm or so ( Fig. 18ah). To establish
the electrical contact between the silicon nanowire gate and the
external gate electrode, an additional step of argon plasma
treatment is needed to physically remove the HfO2 film on the
top half of the nanowires prior to the deposition of the top gate
electrode.
Various type of conducting nanowires (highly doped silicon or
metal silicide, NiSi, PtSi) can be explored for this purpose. For
example, Si/HfO2 coreshell nanowires were recently synthesized
by ALD deposition of 2 nm thick HfO2 on highly doped silicon
nanowires (Fig. 19b and c) [87]. Such coreshell nanowires can be
readily explored for top-gated graphene nanoribbon transistors.
Here theHfO2 shell functionsas thegate dielectrics with controlled
thickness down to 1 nm, and the silicon core functions as the self-
integrated gate. To contact the silicon core gate to external
electrode, the top-half of the HfO2 shell was etched away using
argon plasma. The cross section TEM image clearly shows the
integrated silicon gate, 2-nm thick HfO2 gate dielectric, and thegraphene nanoribbon (Fig. 20b and c).
Electrical transportstudies of the top-gated device were carried
out in ambient conditions at room temperature. The gate
tunnelling leakage current (Igs) from the Si/HfO2 core/shell
nanowire to the underlying GNR is negligible within the gate
voltage range of 1 V range (Fig. 21a). This measurement
demonstrates that the 2 nm thick HfO2 dielectrics can function as
an effective gate insulator for top-gated GNR transistors and afford
high gate capacitance critical to the high transconductance. The
drainsource current (Ids) vs. drainsource voltage (Vds) plots at
various top-gate voltages (VTG) show clearly that the device
conductance decreases as the gate potential increases towards
positive direction (Fig. 21b), demonstrating that the GNR is p-type
doped, which can be attributed to edge oxidation or the physisorbedO2 from ambient or during the device fabrication process. Fig. 21c
shows the transfer characteristics drainsource current (Ids) vs. top-
gated voltage (VTG) curves for the same device at Vds = 0.1 and 1.0 V.
The transfer characteristics show the device can be switched on and
off with
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The transconductancegm = dIds/dVg can be extracted from the IdsVTGcurve. The maximum gm of the top-gated device at Vds = 1 V is about
32mS (Fig. 21e), nearly 20 times largerthan the value obtained in the
back-gated configuration ($1.7mS) (inset, Fig. 21e). Considering the
nanoribbon width $10 nm, the scaled transconductance gm for GNR
transistor reaches$3.2 mS mm1, representing the highest value everreported for GNR transistors.
4.6. Integrated device array from nanowire gated graphene
nanoribbon transistors
The ability to fabricate the top-gated graphene nanoribbon
devices readily allows integration of multiple GNR FETs into
functional device arrays. (Fig. 22a and b), and therefore allowing
for diverse electronic functions. For example, a logic OR gate was
Fig.19. TEM characterization of Si/HfO2 coreshell nanowires. (a)Schematicillustration of thesynthesis of Si/HfO2 coreshell nanowires. Highlydoped p-typesilicon nanowire
arrays were synthesized using catalytic chemical vapour deposition. Atomic layer deposition was used to grow HfO 2 shell with controlled thickness. (b) TEM and (c) HRTEM
images of Si/HfO2 coreshell nanowires. Adapted from [87].
Fig. 20. Characterization of the graphene/HfO2 interface. (a) A SEM image of a typical device. (b) A cross-section TEM image of the top gate stack. (c) A cross-section HRTEM
image of theinterfacebetween nanowires anda multi-layers graphene, which indicate thatthe graphenelayersare intimately integratedwith theSi/HfO2 nanowire without
any obvious gap or impurities between them. A TEM image of multi-layer graphene device is shown here because it is very difficult to visualize the mono- or few-layer of
graphene nanoribbon under the nanowire due to significant electron-beam damage while conducting TEM studies. Adapted from [87].
Fig. 18. Schematic illustration of the fabrication process to obtain top-gated graphene transistors using Si/HfO2 coreshell nanowires as the etchingmask and top-gate. (a and
e) An Si/HfO2 coreshell nanowire is aligned on top of graphene using a dry-transfer process, and the sourcedrain electrodes are fabricated by electron-beam lithography. (b
and f) Oxygen plasma etch is used to remove theunprotected graphene, leaving only the GNR underneath the nanowire connected to two large graphene blocks underneath
thesourceand drain electrodes. (cand g) Thetop-halfof theHfO2 shell wasetchedawayusingargon plasmato exposethe siliconcoregate forcontact toexternalelectrode. (d
and h) The top gate electrode is defined through lithography and metallization process. Adapted from [87].
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Fig. 21. Room temperature electrical properties of the top-gated GNR device by using Si/HfO 2 coreshell as the top-gate. (a) Gate leakage current vs. top-gate voltage. The
leakage current is negligible (atthe nA level) within1 V range.(b) IdsVds output characteristics at variable top-gate voltage starting from 0.6 V at bottom to1.0 Vat top inthe
step of0.2 V. (c) The transfer characteristics IdsVTG at Vds = 0.10 and 1.0 V. (d) IdsVTG and IdsVBG transfer characteristics at Vds = 1 V. (e) Transconductance as a function of top-
gatevoltage VTG andback gatevoltageVBG (inset). (f) Two-dimensional plotof the device conductance at varyingVBG and VTG bias,the unitin thecolor scaleismS. Adapted from [87].
Fig. 22. Independently addressable GNR device array. (a) An SEM image of two independently addressable top-gated GNR FETs. (b) Transfer characteristics of two top-gated
GNR FETsat Vds = 0.1 V. (c)The SEMimageof a logic OR gates built from GNRtransistors.The inset shows theschematic circuitdiagram.(d) TheOR gate outputcharacteristics
with double top-gates. The operating voltage isVdd
= 1 V. The inputs for the two gates, A and B, are 1 V for state 1 and 0 for state 0. Adapted from [88].
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demonstrated with two independent gate electrodes fabricated on
a GNR in conjunction with a loading resistor (Fig. 22c). The OR
function occurs because the output voltage is low only when the
input of both gates is at low voltages (Fig. 22d). When one or both
gates are at high voltages, the GNR channel is electrically shut off,
resulting in a high output voltage.
5. Summary
Graphene is emerging as an interesting electronic material for
future electronics due to their exceptionally high carrier mobility,
tunable band gap and atomically thin structure. The gate dielectric
is an essential component of a transistor and can significantly
impact the critical device parameters including transconductance,
subthreshold swing and frequency response. Exploring graphene
for future electronics requires its effective integration with high
quality gate dielectrics, in particular the high-kdielectrics, which is
of significant challenge due to the intrinsic incompatibility
between pristine graphene and oxide dielectrics. Physical vapour
deposition (PVD) such as electron-beam evaporation or sputtering
process has been used to deposit dielectrics, although the PVD
process usually yields lower quality of dielectrics and can cause
significant damages to graphene. The deposition of high-k
dielectrics using ALD requires reactive surface groups. Functiona-
lization of graphene surface for ALD either introduces undesired
impurities or breaks the chemical bonds in the graphene lattice,
inevitably leading to a significant degradation in carrier mobilities.
As a result, the mobility values observed in the top-gated devices
are typically nearly one order of magnitude smaller than those
achieved in the back-gated devices. Recently, the introduction of
polymer or aluminum buffer layer for high-k deposition has been
demonstrated with improved device mobility, which, however, is
still lower than best values observed in back-gated graphene
devices. A newly developed physical assembly approach to
integrate graphene with free-standing dielectric nanostructures
can minimize potential damage to graphene lattice, and have
enabled the highest mobility top-gated graphene transistors ever.
This methodopens a new avenue to integrate high-k dielectrics ongraphene with the preservation of high carrier mobility. With
further optimization of dielectric nanostructure growth and
assembly process to precisely control their physical dimension
and spatial location, large arrays of top-gated graphene transistors
or circuits can be envisioned. This physical assembly and
integration approach can thus open a new avenue to high
performance graphene electronics, which can impact significantly
high speed high frequency circuits and enable an entirely new
generation of flexible, wearable or disposable electronics for
computing, storage and wireless communication.
References
[1] http://en.wikipedia.org/wiki/Graphene.in.[2] A. Dato, Z. Lee, K.J. Jeon, R. Erni, V. Radmilovic, T.J. Richardson, M. Frenklach,Chemical Communications (2009) 60956097.
[3] A.K. Geim, K.S. Novoselov, Nature Materials 6 (2007) 183191.[4] K.S. Novoselov, A.K. Geim, S.V. Morozov, D. Jiang, Y. Zhang, S.V. Dubonos, I.V.
Grigorieva, A.A. Firsov, Science 306 (2004) 666669.[5] J.S. Bunch, Y. Yaish, M. Brink, K.Bolotin, P.L. McEuen, Nano Letters 5 (2005) 287
290.[6] K.S. Novoselov, A.K. Geim, S.V. Morozov, D. Jiang, M.I. Katsnelson, I.V. Grigorieva,
S.V. Dubonos, A.A. Firsov, Nature 438 (2005) 197200.[7] Y.B. Zhang, Y.W. Tan, H.L. Stormer, P. Kim, Nature 438 (2005) 201204.[8] C. Berger, Z.M. Song, X.B. Li, X.S. Wu, N. Brown, C. Naud, D. Mayou, T.B. Li, J. Hass,
A.N.Marchenkov, E.H.Conrad,P.N. First, W.A.de Heer,Science 312(2006) 11911196.
[9] P. Avouris, Z.H. Chen, V. Perebeinos, Nature Nanotechnology 2 (2007) 605615.[10] Z.H. Chen, Y.M. Lin, M.J. Rooks, P. Avouris, Physica E: 40 (2007) 228232.[11] K.I. Bolotin, K.J. Sikes, Z. Jiang, M. Klima, G. Fudenberg, J. Hone, P. Kim, H.L.
Stormer, Solid State Communications 146 (2008) 351355.[12] X.Du, I. Skachko,A. Barker,E.Y.Andrei,Nature Nanotechnology3 (2008)491495.
[13] F. Miao, S. Wijeratne, Y. Zhang, U.C. Coskun, W. Bao, C.N. Lau,Science 317 (2007)15301533.
[14] D.B. Farmer, H.Y. Chiu, Y.M. Lin, K.A. Jenkins, F.N. Xia, P. Avouris, Nano Letters 9(2009) 44744478.
[15] J.S. Moon, D. Curtis, M. Hu, D. Wong, C. McGuire, P.M. Campbell, G. Jernigan, J.L.Tedesco, B. Vanmil, R. Myers-Ward, C. Eddy, D.K. Gaskill, IEEE Electron DeviceLetters 30 (2009) 3.
[16] A.K. Geim, Science 324 (2009) 15301534.[17] R.V. Gorbachev, A.S. Mayorov, A.K. Savchenko, D.W. Horsell, F. Guinea, Nano
Letters 8 (2008) 19951999.[18] K.F. Mak, C.H. Lui, J. Shan, T.F. Heinz, PhysicalReview Letters 102(2009)256405.
[19] F.Wang, Y.B. Zhang, C.S. Tian,C. Girit, A.Zettl, M.Crommie, Y.R. Shen,Science 320(2008) 206209.[20] Y.B. Zhang, T.T. Tang, C. Girit, Z. Hao, M.C. Martin, A. Zettl, M.F. Crommie, Y.R.
Shen, F. Wang, Nature 459 (2009) 820823.[21] A.C. Ferrari, J.C. Meyer, V. Scardaci, C. Casiraghi, M. Lazzeri, F. Mauri, S. Piscanec,
D. Jiang, K.S. Novoselov, S. Roth, A.K. Geim, Physical Review Letters 97 (2006)187401.
[22] R. Murali, Y.X. Yang, K. Brenner, T. Beck, J.D. Meindl, Applied Physics Letters 94(2009) 243114.
[23] I. Meric, M.Y. Han, A.F. Young, B. Ozyilmaz, P. Kim, K.L. Shepard, NatureNanotechnology 3 (2008) 654659.
[24] Y.M. Lin, H.Y. Chiu, K.A. Jenkins, D.B. Farmer, P. Avouris, A. Valdes-Garcia, IEEEElectron Device Letters 31 (2010) 6870.
[25] Y.M. Lin, C. Dimitrakopoulos, K.A. Jenkins, D.B. Farmer, H.Y. Chiu, A. Grill, P.Avouris, Science 327 (2010) 662.
[26] D.Y. Jeon, K.J. Lee, M. Kim, D.C. Kim, H.J. Chung, Y.S. Woo, S. Seo, Japanese Journalof Applied Physics 48 (2009) 091601.
[27] Y.M. Lin, K.A. Jenkins, A. Valdes-Garcia, J.P. Small, D.B. Farmer, P. Avouris, NanoLetters 9 (2009) 422426.
[28] F.N. Xia, T. Mueller, Y.M. Lin, A. Valdes-Garcia, P. Avouris, Nature Nanotechnol-ogy 4 (2009) 839843.
[29] Y.W. Son, M.L. Cohen, S.G. Louie, Physical Review Letters 97 (2006) 216903.[30] M.Y. Han, B. Ozyilmaz, Y.B. Zhang, P. Kim, Physical Review Letters 98 (2007)
206805.[31] X.L. Li, X.R. Wang, L. Zhang, S.W. Lee, H.J. Dai, Science 319 (2008) 12291232.[32] X.R. Wang,Y.J. Ouyang, X.L. Li,H.L.Wang, J. Guo, H.J. Dai, PhysicalReview Letters
100 (2008) 206803.[33] L.Y. Jiao, L. Zhang, X.R. Wang, G. Diankov, H.J. Dai, Nature 458 (2009) 877880.[34] J.W.Bai, X. Zhong, S. Jiang, Y. Huang, X.F. Duan,Nature Nanotechnology 5 (2010)
190194.[35] J.W. Bai, X.F. Duan, Y. Huang, Nano Letters 9 (2009) 20832087.[36] P.G. Silvestrov, K.B. Efetov, Physical Review Letters 98 (2007) 016802.[37] L.A. Ponomarenko, F. Schedin, M.I. Katsnelson, R. Yang, E.W. Hill, K.S. Novoselov,
A.K. Geim, Science 320 (2008) 356358.[38] D.S.L. Abergel, A. Russell, V.I. Falko, Applied Physics Letters 91 (2007) 063125.[39] P. Blake, E.W. Hill, A.H.C. Neto, K.S. Novoselov, D. Jiang, R. Yang, T.J. Booth, A.K.
Geim, Applied Physics Letters 91 (2007) 063124.[40] Z.H. Ni, H.M. Wang, J. Kasim, H.M. Fan, T. Yu, Y.H. Wu, Y.P. Feng, Z.X. Shen, Nano
Letters 7 (2007) 27582763.[41] S. Roddaro, P. Pingue, V. Piazza, V. Pellegrini, F. Beltram, Nano Letters 7 ( 2007)
27072710.[42] L.B. Gao, W.C. Ren, F. Li, H.M. Cheng, ACS Nano 2 (2008) 16251633.[43] L.Liao,J.W.Bai, Y.Q. Qu,Y. Huang, X.F. Duan,Nanotechnology 21(2010) 015705.[44] X. Hong, A. Posadas, K. Zou, C.H. Ahn, J. Zhu, Physical Review Letters 102 (2009)
136808.[45] J.H. Chen, C. Jang, S.D. Xiao, M. Ishigami, M.S. Fuhrer, Nature Nanotechnology 3
(2008) 206209.[46] F. Chen, J.L. Xia, D.K. Ferry, N.J. Tao, Nano Letters 9 (2009) 25712574.[47] F. Chen, J.L. Xia, N.J. Tao, Nano Letters 9 (2009) 16211625.[48] R.S. Shishir, D.K. Ferry, Journal of Physics-Condensed Matter 21 (2009) 232204.[49] Y.W. Tan, Y. Zhang, K. Bolotin, Y. Zhao, S. Adam, E.H. Hwang, S. Das Sarma, H.L.
Stormer, P. Kim, Physical Review Letters 99 (2007) 246803.[50] K.I. Bolotin, K.J. Sikes, J. Hone, H.L. Stormer, P. Kim, Physical Review Letters 101
(2008) 096802.[51] L.A.Ponomarenko, R. Yang, T.M.Mohiuddin, M.I. Katsnelson, K.S. Novoselov, S.V.
Morozov, A.A. Zhukov, F. Schedin, E.W. Hill, A.K. Geim, Physical Review Letters
102 (2009) 206603.[52] F. Peter, K. Szot, R. Waser, B. Reichenberg, S. Tiedke, J. Szade, Applied PhysicsLetters 85 (2004) 28962898.
[53] Y. Huang, X.F. Duan, Y.Cui, L.J. Lauhon, K.H. Kim, C.M. Lieber, Science 294 (2001)13131317.
[54] A. Javey, H. Kim, M. Brink, Q. Wang, A. Ural, J. Guo, P. McIntyre, P. McEuen, M.Lundstrom, H.J. Dai, Nature Materials 1 (2002) 241246.
[55] S.J.Wind, J. Appenzeller, R. Martel, V. Derycke, P. Avouris,Applied Physics Letters80 (2002) 38173819.
[56] C. Berger, Z.M. Song, T.B. Li, X.B. Li, A.Y. Ogbazghi, R. Feng, Z.T. Dai, A.N.Marchenkov, E.H. Conrad, P.N. First, W.A. de Heer, Journal of Physical ChemistryB 108 (2004) 1991219916.
[57] G. Gu, S. Nie, R.M. Feenstra, R.P. Devaty, W.J. Choyke, W.K. Chan, M.G. Kane,Applied Physics Letters 90 (2007) 253507.
[58] M.C. Lemme, T.J. Echtermeyer, M. Baus, H. Kurz, IEEE Electron Device Letters 28(2007) 282284.
[59] A. Das, S. Pisana, B. Chakraborty, S. Piscanec, S.K. Saha, U.V. Waghmare, K.S.Novoselov, H.R. Krishnamurthy, A.K. Geim, A.C. Ferrari, A.K. Sood, Nature Nano-technology 3 (2008) 210215.
L. Liao, X. Duan/ Materials Science and Engineering R 70 (2010) 354370 369
http://en.wikipedia.org/wiki/Graphene.inhttp://en.wikipedia.org/wiki/Graphene.in -
8/3/2019 artigo grafeno
17/17
[60] J. Kedzierski, P.L. Hsu, P. Healey, P.W. Wyatt, C.L. Keast, M. Sprinkle, C. Berger,W.A. de Heer, IEEE Transactions on Electron Devices 55 (2008) 20782085.
[61] Y.Q. Wu, P.D. Ye, M.A. Capano, Y. Xuan, Y. Sui, M. Qi, J.A. Cooper, T. Shen, D.Pandey, G. Prakash, R. Reifenberger, Applied Physics Letters 92 (2008) 092102.
[62] Z.H. Ni,H.M.Wang, Y.Ma, J. Kasim,Y.H.Wu, Z.X. Shen, ACSNano2 (2008)10331039.
[63] J. Robertson, Reports on Progress in Physics 69 (2006) 327396.[64] B.K. Lee, S.Y. Park, H.C. Kim, K. Cho, E.M. Vogel, M.J. Kim, R.M. Wallace, J.Y. Kim,
Applied Physics Letters 92 (2008) 203102.[65] F.H. Yang, R.T. Yang, Carbon 40 (2002) 437444.[66] Y.Xuan, Y.Q. Wu,T. Shen,M. Qi,M.A.Capano, J.A. Cooper,P.D.Ye, Applied Physics
Letters 92 (2008) 013101.[67] D.B. Farmer, R.G. Gordon, Nano Letters 6 (2006) 699703.[68] M. Leskela, M. Ritala, Thin Solid Films 409 (2002) 138146.[69] A. Hashimoto, K. Suenaga, A. Gloter, K. Urita, S. Iijima, Nature 430 (2004) 870
873.[70] J.R. Williams, L. DiCarlo, C.M. Marcus, Science 317 (2007) 638641.[71] Y.M. Lin, V. Perebeinos, Z.H. Chen, P. Avouris, Physical Review B 78 (2008)
161409.[72] M.C. Lemme, T.J. Echtermeyer, M. Baus, B.N. Szafranek, J. Bolten, M. Schmidt, T.
Wahlbrink, H. Kurz, Solid-State Electronics 52 (2008) 514518.[73] X.R. Wang, S.M. Tabakman, H.J. Dai, Journal of The American Chemical Society
130 (2008) 81528153.[74] M.D. Groner, F.H. Fabreguette, J.W. Elam, S.M. George, Chemistry of Materials 16
(2004) 639645.[75] A. Hoshino,S. Isoda, H. Kurata, T. Kobayashi, Journal of Applied Physics 76 (1994)
41134120.[76] J.R. Ostrick, A. Dodabalapur, L. Torsi, A.J. Lovinger, E.W. Kwock, T.M. Miller, M.
Galvin, M. Berggren, H.E. Katz, Journal of Applied Physics 81 (1997) 68046808.
[77] S. Kim, J. Nah, I. Jo, D. Shahrjerdi, L. Colombo, Z. Yao, E. Tutuc, S.K. Banerjee,Applied Physics Letters 94 (2009) 062107.
[78] M.J. Dignam, W.R. Fawcett, H. Bohni, Journal of The Electrochemical Society 113(1966) 656657.
[79] C.C. Chang, D.B. Fraser, M.J. Grieco, T.T. Sheng, S.E. Haszko, R.E. Kerwin, R.B.Marcus, A.K. Sinha, Journal of The Electrochemical Society 125 (1978) 787792.
[80] M. Ishigami, J.H. Chen, W.G. Cullen, M.S. Fuhrer, E.D. Williams, Nano Letters 7(2007) 16431648.
[81] S. Adam, E.H. Hwang, V.M. Galitski, S. Das Sarma, Proceedings of the NationalAcademy of Sciences of the United States of America 104 (2007) 1839218397.
[82] W.H. Wang, W. Han, K. Pi, K.M. McCreary, F. Miao, W. Bao, C.N. Lau, R.K.Kawakami, Applied Physics Letters 93 (2008) 183107.
[83] D.B. Farmer, R. Golizadeh-Mojarad, V. Perebeinos, Y.M. Lin, G.S. Tulevski, J.C.Tsang, P. Avouris, Nano Letters 9 (2009) 388392.
[84] B. Huard, N. Stander, J.A. Sulpizio, D. Goldhaber-Gordon, Physical Review B 78(2008) 121402.
[85] S.V. Morozov, K.S. Novoselov, M.I. Katsnelson, F. Schedin, D.C. Elias, J.A. Jaszczak,A.K. Geim, Physical Review Letters 100 (2008) 016602.
[86] A. Barreiro, M. Lazzeri, J. Moser, F. Mauri, A. Bachtold, Physical Review Letters
103 (2009) 076601.[87] L. Liao, J.W. Bai, R. Cheng, Y.C. Lin, S. Jiang, Y. Huang, X.F. Duan, Nano Letters 10(2010) 19171921.
[88] L. Liao, J.W. Bai, Y.C. Lin, Y.Q. Qu, Y. Huang, X.F. Duan, Advanced Materials 22(2010) 19411945.
[89] L. Liao, J.W. Bai, Y.Q. Qu, Y.C. Lin, Y.J. Li, Y. Huang, X.F. Duan, Proceedings of theNational Academy of Sciences of the United States of America 107 (2010) 67116715.
[90] D. Whang, S. Jin, Y. Wu, C.M. Lieber, Nano Letters 3 (2003) 12551259.[91] A. Tao, F. Kim, C. Hess, J. Goldberger, R.R. He, Y.G. Sun, Y.N. Xia, P.D. Yang, Nano
Letters 3 (2003) 12291233.[92] X.F. Duan, C.M. Niu, V. Sahi, J. Chen, J.W. Parce, S. Empedocles, J.L. Goldman,
Nature 425 (2003) 274278.[93] J.A. Rogers, R.G. Nuzzo, Materials Today 8 (2005) 5056.[94] M.D. Groner, J.W. Elam, F.H. Fabreguette, S.M. George, Thin Solid Films 413
(2002) 186197.[95] X.S. Fang, C.H. Ye, X.S. Peng, Y.H. Wang, Y.C. Wu, L.D. Zhang, Journal of Materials
Chemistry 13 (2003) 30403043.[96] V.V.Afanasev, M. Houssa, A. Stesmans, G.J.Adriaenssens, M.M.Heyns, Journal of
Non-Crystalline Solids 303 (2002) 6977.[97] C.M. Perkins, B.B. Triplett, P.C. McIntyre, K.C. Saraswat, E. Shero, Applied Physics
Letters 81 (2002) 14171419.[98] Y.C. Yeo, T.J. King, C.M. Hu, Journal of Applied Physics 92 (2002) 72667271.[99] X.R. Wang, X.L. Li, L. Zhang, Y. Yoon, P.K. Weber, H.L. Wang, J. Guo, H.J. Dai,
Science 324 (2009) 768771.[100] R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, M. Metz, IEEE Electron Device
Letters 25 (2004) 408410.
L. Liao, X. Duan/ Materials Science and Engineering R 70 (2010) 354370370