Semana 4 - Lecciones

4 1 BLOQUES ARITMTICOS4 .1Elena ValderramaUniversidad Autnoma de Barcelona

4 .1

Losbloquesaritmticosconstituyenunaparteimportanteencasocualquiercircuitodigital.

1.SUMA

2 RESTA

Estudiaremoscircuitoscapacesdeimplementarlas4operacionesbsicas:

2.RESTA

3.MULTIPLICACIN

4.DIVISIN

2

1.Sumabinaria4 .1

Sumadorparalelo:Verlecciones2.2y2.3delasemana2.

xi yi

Sumador1bit acarreoINacarreoOUT

Sumadorn bits

Sumadorn bits

n

nn+1

acarreo01

zi

xn-1 yn-1 x1 y1 x0 y0xn-2 yn-2

Full_Adder (FA)

Sumador1bitacarreoOUT

Sumador1bit

Sumador1bit

Sumador1bit acarreoIN

zn-1 zn-2 z1 z03

2.Restabinaria4 .1

Unrestadorbinariorealizaelclculo:

RestadorRestadorn

n+1Restadorn bits

Restadorn bits

n n+1

acarreo01donde:

acarreo0:1bit(habitualmente igual a 0)

Cmorepresentamosunnmeronegativo?

SiD

2.Restabinaria4 .1

Algoritmomanual:1 1 0 0 1 0 0 11 0 0 1 1 1 0 0

n pasos,encadapasocalculamos: Elbitresta:

1 0 0 1 1 1 0 0

Elacarreohacialaetapasiguiente:g

5

4 .12.Restabinaria

Algoritmo1delarestaacarreo(0)

4 .12.Restabinaria n

Restadorn bits

Restadorn bits

nn+1

acarreo01xi yi

d(i)

(Ejercicio)4 .1

(Ejercicio)

ConstruiruncircuitoquecalculeD =x y (x,y den bits)ydevuelvaelvalordeD enlarepresentacin clsica de signo y magnitud, es decir, como D = (1)sign|D|representacinclsicade signoymagnitud ,esdecir,comoD ( 1) |D|

Sugerencia:Calculaenparalelox y andy x yseleccionael|D|dependiendodelsignodex y.

8

(Solucin del ejercicio)4 .1

(Solucindelejercicio)

ConstruiruncircuitoquecalculeD =x y (x,y den bits)ydevuelvaelvalordeD enlarepresentacinclsicadesignoymagnitud,esdecir,comoD =(1)sign|D|p g y g , , ( ) | |

Sugerencia:CalculaenparaleloX Y andY X yseleccionael|D|dependiendodelsignodeX Y.

x y y x

subtract. 0 subtract. 0

d d

Restador Restador

10

d d

dsign9

4 .13.Multiplicadorbinario

Unmultiplicadorrealizaelclculo:

Algoritmo1:

X

donde:

p0 =Xy0;p1 =Xy12;p2 =Xy222;MayorvalordeP: pm1 =Xym12m1;

P =p0 +p1 +p2 ++pm1 .

P esunnmeroden+m bits

10

4 .13.Multiplicadorbinario

Ej l

Algoritmo1:

p0 =Xy0;Ejemplo:

101101x1011

p1 =Xy12;p2 =Xy222;

1101101 p0101101 p1000000

pm1 =Xym12m1;

P =p0 +p1 +p2 ++pm1 .

000000 p2101101 p3111101111 P

11

4 .13.Multiplicadorbinariop0 =Xy0;p1 =Xy12;p2 =Xy222;pm1 =Xym12m1;

P =p0 +p1 +p2 ++pm1 .

Algoritmo2:Righttoleft algorithm

acc

4 .14.Divisorbinario

DadosdosnmerosX eY naturales(X

4 .14.DivisorbinarioAlgoritmodedivisinbinaria

r(0)

4 .1RESUMEN

Hemosvistounconjuntodecircuitoscapacesdeejecutarlasoperacionesaritmticasbsicasdesuma,resta,multiplicacinydivisin.

Hemosintroducido,aunquemuybrevemente,larepresentacindenmerosnegativosmedianteelcomplementoa2.

16

4 2 Short introduction to VHDL4 .2Llus TersInstituto de Microelectrnica de Barcelona, IMB-CNM (CSIC)Universitat Autnoma de Barcelona (UAB)Universitat Autnoma de Barcelona (UAB)

CONTENTS

1 M i l & E t d l i

4 .21. Maingoals&Expectedlearning2. BasicsonVHDLlexical&syntax3. VHDLDesignUnits4 VHDL Sequential Sentences (selection)4. VHDLSequentialSentences(selection)5. VHDLConcurrentSentences(selection)6. VHDLusageformodelling,simulationandsynthesis7 Summary7. Summary

18

Main goals & Expected learning

M i l

.24Maingoals

VHDLsyntax,mainunitsandstructure Fundamentalsonsequentialandconcurrentstatements

Processes Componentinstances Signalassignments

VHDLusage:modelling,simulationandsynthesis

Expectedlearning BasicknowledgeaboutVHDLlanguageanditsusage(basedonexamplesalreadyseeninthiscourse) BeabletoreadandunderstandsimpleVHDLcode BeabletowritespecificportionsofVHDLcode Understandtheroleofhardwarelanguagesindigitalsystemsdesign

19

Basics on VHDL lexical & syntax

Lexicalelements:ReservedWords,Identifiers,Symbols,Literals

.24, , y ,

Language Reserved Wordsabs access after alias all and architecturearray assert attribute begin block body bufferbus case component else elsif end entitybus case component else elsif end entityexit file for function generate generic guardedif in inout is label library nandnew next nor not null of onopen or others out process procedure ...

Identifiers to provide specific names to VHDL elements and objects- Based on character set {az, AZ, 09, _}- First character shall be alphabetical and _ at the end or two __ are forbidden- Upper/lower-case are indifferent and reserved words are forbiddenExamples: COUNT, aBc, X, f123, VHDL, VH_DL, ABC, q1, Q0

Symbols- 1 or 2 characters- operators, punctuation, comments, part of sent.

LiteralesBase Character Physical2#110_1010# a A @ 10 ns

+ - * / ( ) . , : & < > = | # ; -- => ** := /= >=

Basics on VHDL lexical & syntax

VHDLObjects

.24j

VHDLobjectisanylanguageelementabletocontainavalue TypesofVHDLobjects:

ConstantConstant Variable Signal File

Object definition: : [:= Initial value];

File

constant PI : real := 3.1415927; constant WordBits : natural := 8;constant NumWords : natural := 1024;

t t T tBit t l W dBit * N W d

Variables declaration

variable Counter : integer :=0;variable Increment : integer;

I t 2 V i blconstant TotBits : natural := WordBits * NumWords; Increment := 2;Counter := Counter + Increment;

Variables assignment

signal Clk : bit := 0;...Clk < 1

Signal declaration& initializationSi l i tClk

4Basics on VHDL lexical & syntax .2VHDLDataTypes

TheVHDLisastronglytypedlanguage Adatatypedefinesasetoffixedandstaticvalues Anylanguageobjectbelongstoaspecificdatatype Objectvaluesshallbelongtorelateddatatype Newdatatypescouldbeuserdefinedtype boolean is (false, true);

type bit is (0, 1);type severity_level is (note, warning, error, failure);

STANDARD package: Predefined Types of VHDL

type character is (NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS, HT, LF, VT, FF, CR, SO, SI, DEL, DC1, DC2, DC3, DC4, DC5, NAK, SYN, ETB, CAN, EM, SUB, ESC, FSP, GSP, RSP, USP, , !, , #, $, %, &, , (, ), *, +, ,. -, ., /, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, :, ;, , ?, @, A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V,W, X, Y, Z, [, \, ], ^, _, `, a, b, c,d, e, f, g, h, i, j, k, l, m, n, o, p,

q, r, s, t, u, v, w, x, y, z, {, ...);type integer is range -2.147.483.647 to 2.147.483.647;type real is range -1.0e38 to 1.0e38;/ 22

4Basics on VHDL lexical & syntax .2VHDLDataTypesyp

TheVHDLisastronglytypedlanguage Adatatypedefinesasetoffixedandstaticvalues Any language object belongs to a specific data typeAnylanguageobjectbelongstoaspecificdatatype Objectvaluesshallbelongtorelateddatatype Newdatatypescouldbeuserdefined

type time is range 0 to 1e20unitsfs;ps = 1000 fs;ns = 1000 ps;ns 1000 ps;us = 1000 ns;ms = 1000 us;sec = 1000 ms;min = 60 sec;h 60 ihr = 60 min;end units time;

23

Basics on VHDL lexical & syntax .2VHDLOperatorsandexpressions

4 Operatorsaresymbolsidentifyingspecificoperations Types:arithmetic,logic,relationalandconcatenation Operands: Expressions:

Relational

=/=

Logic

andor

Arithmetic

+

Arithmetic(-b + sqrt(b**2 - 4.0*a*c))/(2.0*a)

/== 20 nsname < Smith

Logic(a xor b) and not c;

>>=

xornot

**modremabsConcatenation

ConcatenationBitSign & VectorValue

Expressionscouldbeassignedto:absConcatenation

&

p g Constants(const := expression;) Variables(var := expression;) Signals(sig

VHDL Design Units .2VHDLisorganizedondifferentDesignUnits:

4 Entity Architecture Package(declaration&body) Configuration

EntityDeclaration

ConfigurationD l i

PackageDeclaration

PrimDeclaration Declaration Declaration

mary

PackageArchitecture

Secund

gBody1

Architecture2 dary

Architecturen 25

VHDL Design Units .2ENTITY

4 Likeablackboxjustdescribingexternalinterfaceforamodulewhile

hidingitsinternalarchitecture Syntax:

entity is[];[];

Entity name (module name)

Generic parameters

Input/Output ports (electrical interface)p[];

[begin ];end [entity] [];

Input/Output ports (electrical interface)

Global declarations (common to any potential architecture of this entity)

Passive sentences (common to any potential architecture of this entity)

MUX21AB Z

entity MUX21 isport( A : in bit;

B : in bit;Ct l i bit MUX21B

CtrlZCtrl : in bit;

Z : out bit;end MUX21;

26

VHDL Design Units .2ENTITY

4 Likeablackboxjustdescribingexternalinterfaceforamodulewhile

hidingitsinternalbehaviourandarchitecture Syntax:

entity is[];[];

Entity name (module name)

Generic parameters

Input/Output ports (electrical interface)p[];

[begin ];end [entity] [];

Input/Output ports (electrical interface)

Global declarations (common to any potential architecture of this entity)

Passive sentences (common to any potential architecture of this entity)

nA

n n

entity MUX21n isgeneric( n : integer := 2);port( A : in bit_vector(n-1 downto 0);

B : in bit vector(n-1 downto 0);

Bus size as generic parameter

MUX21BCtrl

Zn nB : in bit_vector(n 1 downto 0);

Ctrl : in bit;Z : out bit_vector(n-1 downto 0));

end MUX21; 27

VHDL Design Units .2ARCHITECTURE

4 DetailswhatisbehindanEntitywhiledescribingitsbehaviouratfunctional,

dataflow,structuralormixedlevels MultipleArchitecturesfo asingleEntityarepossible Syntax:

Architecture nameE tit

architectura of is[];

begin;

Signals, variables, components

Concurrent sentences: Concurrent assignments

Entity name

end [architecture] []; Concurrent assignments Instances to components Processes Blocks

28

VHDL Design Units: Entity & Architectures .24entity MUX21 is

port( A, B, Ctrl : in bit;Z : out bit);

end MUX21;

entity MUX21n isgeneric ( n: natural);port( A : in bit_vector(n-1 downto 0);

B : in bit_vector(n-1 downto 0);Ctrl : in bit;

architecture Functional of MUX21 isbegin

process(A, B, Ctrl)begin

Ctrl : in bit;Z : out bit_vector(n-1 downto 0));

end MUX21;

architecture Functional of MUX21n isbegif Ctrl = 0 then

Z

VHDL Design Units : Entity & Architectures .2entity MUX21 is

i i

4port( A : in bit;

B : in bit;Ctrl : in bit;Z : out bit;

end MUX21;

architecture structural of MUX21 issignal Ctrl_n, N1, N2 : bit;component INV;

port( Y : in bit;Z : out bit);

end component;component AND2

port( X, Y : in bit;

architecture DataFlow of MUX21 issignal Ctrl_n, N1, N2 : bit;

b i

p ( , ;Z : out bit);

end component;component OR2

port( X, Y : in bit;Z : out bit);begin

Ctrl_n

VHDL Design Units .2PACKAGE

4 Usefulforcodereuseasitcouldcontaindefinitionsofdatatypes,functionsand

languageobjects(constants,variables,signalsorfiles)foritsuseondifferentcodes Twounits:

P k Packagedeclaration package

[];end [package] []

Package name

Declarations of: Data types Constants

Packagebody

Functions & procedures

package body [

VHDL Design Units .2PACKAGE

VHDL constant object Constant Id Constant Comment

4package VSuP_Pack is

-- Processor basic dimensionsconstant ProcWordBits : integer; -- Processor word lenght (bits)

VHDL constant object Constant Id. data type Comment

constant MemAdrBits : integer; -- Memory address lenght (bits)constant CtrlBusNumBits : integer; -- Number of bits for control busconstant StatusBusNumBits : integer; -- Number of bits for status and flags busconstant ALUopNumBits : integer; -- Number of bits to especify the ALU operation codeconstant OpCodeNumBits : integer; -- Number of bits to especify the instruction OpCodep g p y pconstant Bus2zeros : std_ulogic_vector (ProcWordBits-1 downto 0); -- constant string of 0sconstant Bus2ones : std_ulogic_vector (ProcWordBits-1 downto 0); -- constant string of 1sconstant One : std_ulogic_vector (ProcWordBits-1 downto 0); -- constant value 1;

-- Mnemonics for ALU operationsMnemonics for ALU operationsconstant NoOp,Add,Sub,IncL,IncR,DecL,DecR,AndL,

OrL,NotL,LSh,RRot,GoL,GoR,Out0,Out1 : std_ulogic_vector (ALUopNumBits-1 downto 0);

-- Processor instruction set OpCodest t S O S C S O O S Oconstant LDA, STA,MOV,SAV,CLR,SET,LAND,LNOT,LOR,SHIL,ROTR,ADD,SUB,INC,DEC,CMP,BRZ,BRN,JMP,NOP,EOP : std_ulogic_vector (OpCodeNumBits-1 downto 0);

end package VSuP_Pack; 32

VHDL Design Units .2PACKAGEpackage body VSuP_Pack is

-- Processor basic dimensions

Constant values definition. 4-- Processor basic dimensionsconstant ProcWordBits : integer := 16; -- Processor word lenght (bits)constant MemAdrBits : integer := 16; -- Memory address lenght (bits)constant CtrlBusNumBits : integer := 25; -- Number of bits for control busconstant StatusBusNumBits : integer := 5; -- Number of bits for status and flags busconstant ALUopNumBits : integer := 4; -- Number of bits to especify the ALU operation codeconstant OpCodeNumBits : integer := 5; -- Number of bits to especify the instruction OpCodeconstant Bus2zeros : std_ulogic_vector (ProcWordBits-1 downto 0):= (others =>0);constant Bus2ones : std_ulogic_vector (ProcWordBits-1 downto 0):= (others =>1);constant One : std ulogic vector (ProcWordBits-1 downto 0) := conv std logic vector (1, _ g _ ( ) _ _ g _ ( ,

ProcWordBits); -- Mnemonics for ALU operations-- No operation cycleconstant NoOp : std_ulogic_vector (ALUopNumBits-1 downto 0) := "0000";-- Addition: Out

VHDL Summary (part-I) .2Sessionsummary

4 BasicsonVHDLlexicalandsyntax

Languagelexicalelements

Objects (constant variable signal and files) Objects(constant,variable,signalandfiles)

Datatypes,Operatorsandexpressions

VHDLdesignunits

EntityandArchitecture

Configuration

Package (declaration & body)Package(declaration&body)

SimplifiedformalVHDLdesignunitsdescriptionsbutexamplebasedlearning

34

4 3 Short introduction to VHDL (cont.)4 .3Llus TersInstituto de Microelectrnica de Barcelona, IMB-CNM (CSIC)Universitat Autnoma de Barcelona (UAB)Universitat Autnoma de Barcelona (UAB)

VHDL Sentences (selected subset) .3Sequentialvs.ConcurrentSentences

4 Sequential

AlgorithmicsentenceslikeforSWlanguages(if, case, loop, exit, return, ) Interpretedsequentially Orderofsentencesisimportantfortheresults

Onlyusedinfunctions,proceduresandProcesses Concurrent

Devotedtoexpresshardwarestructure(Hw componentsandblocksaredoingconcurrently)d ki i l landprocessesworkingsimultaneously

Somesequentialsentenceshaveitsequivalentconcurrentones Selectedsentences:Process,Signalassignments,Componentsinstantiation Mainly used in Architectures MainlyusedinArchitectures

ConcurrenttoSequentialforsimulation EachconcurrentstatementcouldbetranslatedtoitsequivalentProcess basedonsequential

statements. Forsimulationpurposesalltheconcurrentstatementsaretranslatedtorelatedprocesses. VHDLeventdrivensimulationwillmanagejustalotofprocesses.

36

VHDL Sentences (small selection) .3SequentialSentences

4 Wherearepossible?

processbegin

function F() returnbegin

procedure P() isbegin

-- sequential-- sentencesend process;

-- sequential-- sentencesend F;

-- sequential-- sentencesend P;

Whicharetheselectedsentences? Variable&Signalassignments Wait Ifthenelseendif Case Loop,ExitandNext Functions & Procedures Functions&Procedures Assertreportseverity

37

VHDL Sentences (small selection) .3SequentialSentences:VariableAssignment

4 Immediate replacementofvariablevalue. Syntax:

[label:] := ;

Examples:Var := 0;Vector := 00011100;string := Message is: ;A := B;B := my_function(3,databus)C := my function(4 adrbus) + A;C := my_function(4,adrbus) + A;

38

VHDL Sentences (small selection) .3SequentialSentences:SignalAssignment t t0 t1 ti

4 Projectsanewevent(value,time)onthesignaldriver. Syntax:

[label:]

VHDL Sentences (small selection) .3SequentialSentences:Wait Indicates the point where a process execution shall be suspended as well as the

4 Indicatesthepointwhereaprocessexecutionshallbesuspended,aswellasthe

conditionsforitsreactivation.Morethanonewaitsentenceperprocessispossible. Syntax:

[label:] wait [on {, ...}]

B i l

[until ][for ];

processbegin

Basicexamples:

processbegin

processbegin

c

VHDL Sentences (small selection) .3SequentialSentences:Ifthenelseendif;

4 SelectsthegroupofsentencestoexecutedependingonaBooleancondition. Syntax:

[label:] if then

[label:] if then

{elsif then

VHDL Sentences (small selection) .3SequentialSentences:Case

4 Selectsthegroupofsentencestoexecute

dependingonaexpressionvalue. Syntax:

[label:] case is{when =>;}[when others =>;]

Orofvalues:when00|01 Valuesrange:when5to12(integers) Lastoption:whenothers

;]end case [label];

t kd (M d T d W d d Th d F id S t d S d ) Examples:

processbegin

D i

type weekdays : (Monday, Tuesday, Wednesday, Thursday, Friday, Saturday, Sunday);type typeofday : (Workingday, Holiday);Signal Day : Weekdays;Signal Daytype : typeofday; process

beginV lE t icase Day is

when Monday to Friday =>Daytype Daytype Res := 5;when 1 | 2 | 8 => Res := ValEnt;when 3 to 7 => Res := ValEnt + 5;when others => Res := 0;

end case;wait on Day;

end process;

end case;wait on ValEnt;

end process; 42

4VHDL Sentences (small selection) .3SequentialSentences:If&Case

entity LatMux isport(

Load : in bit;A B C D : in bit;

PreviousexamplewithtwoProcess: Mux Latch

A, B, C, D : in bit;Ctrl : in bit_vector(0 to 1);Y : out bit);

end LatMux;

architecture TwoProc of LatMux isarchitecture TwoProc of LatMux isSignal X : bit;begin

Mux: process (Ctrl, A, B, C, D);begin

case Ctrl isA

LatMux Concurrent Statements

case Ctrl iswhen 00 => X X X X

VHDL Sentences (small selection) .3SequentialSentences:Loop

4 Sequentialsentencesintheloopregionarerepeatedforanumberoftimes. Typesofloops:while,forandwithoutiterationscontrol(infiniteloop). Syntax: [label:] [while | for ] [ abe :] [ e boo ea _co d t o | o epet t o _co t o ]

loop}

end loop [label]; achitecture Functional of ParallelAdder isbegin

Examples:Fulladder

entity ParallelAdder isgeneric (n : natural :=4 );

process (X, Y, Cin);variable C : std_logic_vector(n downto 0);variable tmp : std_logic;variable I : integer;begingeneric (n : natural :=4 );

port ( X, Y : in std_logic_vector(n-1 downto 0);

Cin : in std_logic;Z : out std_logic_vector(n-1 downto 0);

gC(0) := Cin;for I in 0 to n-1 loop

tmp := X(I) xor Y(I);Z(I)

VHDL Sentences (small selection) .34SequentialSentences:Exit(insidealoop) Endstheloopexecutionwhenboolean_conditionistrueandgoestonextsentence

aftertheloop. Syntax: [label:] exit [loop_label] [when ];

N d d f t d l t id tif hi h i th

SequentialSentences:Next(insidealoop)St t l it ti h b l diti i t d f th t it ti

Needed for neested loops toidentify which is theloop tobeexitedor nexted

Stopscurrentloopiterationwhenboolean_conditionistrueandgoesforthenextiteration(skipscurrentiterationafterthissentence).

Syntax: [label:] next [loop_label] [when ];

45

VHDL Sentences (small selection) .3SequentialSentences:Functions(sameassoftwarelanguages)

4 Apieceofcodedevotedtospecificcomputationofinputparameterstoreturnavalue. Syntaxforfunctiondeclaration: function [()] return ;

Syntaxforfunctiondefinition:function [()] return is

{}begin

Example:

{}end [function] [];

[label:] return [expresion];

p

Var := base + bv2int(adrBus(15 downto 8));

function bv2int (bs: bit_vector(7 downto 0)) return integer;

Var : base + bv2int(adrBus(15 downto 8));

Sig

VHDL Sentences (small selection) .3SequentialSentences:Procedures(sameassoftwarelanguages)

4 Apieceofcodedevotedtospecificcomputationofinputparameterstoreturnavalue. Syntaxforproceduredeclaration:

procedure [()];

Syntaxforproceduredefinition:procedure [()] is

{}begin

Example:

{}end [function] [];

pprocedure bv2int (bs: bit_vector(7 downto 0); x: out integer );

bv2int(adrBus(15 downto 8); Var); Var := base + Var;

Procedureusageorreference

47

VHDL Sentences (small selection) .3SequentialSentences:Assert

4

Akindofvalidationsentence:whenisFALSEtheisprintedoutandactionsrelatedtospecifiedseveritylevelaredone.

Syntax: [label:] assert y

Examples:

p[report ][severity (note | warning | error |failure);

passert not(addr < X"00001000" or addr > X"0000FFFF)

report Address in range" severity note;

assert (J /= C) report "J = C" severity note;

SequentialSentences:Report Syntax: [label:] [report < string of characters >]

[severity (note | warning | error |failure);

Example:

[severity (note | warning | error |failure);

report Check point 13; assert FALSE Check point 13 severity note;=

VHDL Summary (part-II) .3Sessionsummary

4 Sequentialvs.ConcurrentworldsinVHDL

VHDLsequentialsentences(insideaprocess,functionorprocedure)

Selected sentences: Selectedsentences:

ExamplesbasedVHDLlearning

Variable&signalassignments Wait

Ifthenelseendif Case

Loop,ExitandNext Assert,Functions&Procedures

49

4 4 Short introduction to VHDL (cont.)4 .4Llus TersInstituto de Microelectrnica de Barcelona, IMB-CNM (CSIC)Universitat Autnoma de Barcelona (UAB)Universitat Autnoma de Barcelona (UAB)

Previous comment .44GeneralstructureofaVHDLmodel

entity X isbeginend X;

S

CONTENTS

1 M i l & E t d l i

.441. Maingoals&Expectedlearning2. BasicsonVHDLlexical&syntax3. VHDLDesignUnits4 VHDL Sequential Sentences (selection)4. VHDLSequentialSentences(selection)5. VHDLConcurrentSentences(selection)6. VHDLusageformodelling,simulationandsynthesis7 Summary7. Summary

53

VHDL Sentences (small selection) .4ConcurrentSentences

4 Alltheconcurrentsentencesarebeingevaluatedsimultaneously

Wherearepossible? Concurrent sentencesentity X is Entity(passivesentences) Block(collectsconcurrentsentences) Architecture

begin

end X;

Whicharetheselectedsentences? Process Signal assignments

architecture Y of X isbegin

B : blockbegin

Signalassignments DirectAssignment ConditionalAssignment SelectedAssignment

end Y;end block;

Components Generate

Eachconcurrentsentencewillbetranslatedtoitsequivalentprocessbeforeitssimulation 54

VHDL Sentences (small selection) .4ConcurrentSentences:Process

4 Containssequentialsentencestodefineitsownbehaviour Communicateswithotherprocessesandconcurrentsentencesbymeansofsignals Theprocessisaninfiniteexecutionloopabletocontainstop/waitconditions(atleastONE!!) Eachprocessissensibletoeventsonspecificsignalsorconditionstolaunchagainitsexecution Syntax:

[:] process [( { })] [is][:] process [( ,{, ...})] [is]

begin

end process [];

process begin

i l

process ()begin

wait on ;

end process;

g

end process;=

55

VHDL Sentences (small selection) .4ConcurrentSentences:SignalAssignment

4 Syntax:

[label:]

VHDL Sentences (small selection) .4ConcurrentSentences:ConditionalSignalAssignment

4g g

Syntax:[:] [when ];

Example process (Sel, A, B)begin

S

VHDL Sentences (small selection) .4ConcurrentSentences:SelectedSignalAssignment

4 Syntax:

[] with select h < l >

Example

when ;

process (Op1, Op2, Operation)begin

case Operation iswhen add => Result Result

VHDL Sentences (small selection) .4ConcurrentSentences:Components

4 Structuralandhierarchicaldescriptionsbyusingcomponentsdefinedsomewhereelse. Syntaxforcomponentdeclaration:

component [is][generic ();]

Syntaxforcomponentreferenceorinstantiation:

[port ();]end [component] [];

: [generic map ();][port map ();]

Examples:

U2 : example port map (X, Y, W, Z)component example ist( b i bit

Association lists by: position name

U4 : example port map(d=>Z, a=>X, b=>Y, c=>W);

port(a, b, c : in bit;d : out bit);

end component example;

name

59

VHDL Sentences (small selection) .4ConcurrentSentences:Components

4

entity FullAdder isbegin

port(X, Y, CIn : in bit;Cout, Sum : out bit); A

U1 U3Cout, Su : out b t);

end FullAdder;

architecture structural of FullAdder iscomponent HalfAdder

t(I1 I2 i td l i

Half Adder Half

Adder

XY

CIn Sum

COutA

B C OrG

port(I1, I2 : in std_logic;COut, Sum : out std_logic);

end component;component OrG

port(I1, I2 : in std_logic;

CIn SumU2

I1 I2 Sum CoutO : out std_logic);

end component;signal A, B, C : std_logic;

beginU1: HalfAdder port map (X, Y, A, B);

Positionalassociationlist0 0 0 00 1 1 01 0 1 01 1 0 1

U1: HalfAdder port map (X, Y, A, B);U2: HalfAdder port map (B, CIn, C, Sum);U3: OrG port map (O => COut, I1 => A, I2 => C);

end structural;Nominalassociationlist

Sum

VHDL Sentences (small selection) .4ConcurrentSentences:Generate

4 Generallyusedtocreatearraysofcomponentinstances,butitcouldincludeanyother

concurrentsentence. Syntax:

: {[for | if ]}generate

{}end generate; entity Register is

generic (N: positive);port( Clk : in std_logic;

E : in std_logic_vector(N-1 downto 0);S out std logic vector(N-1 downto 0));

Parallelin/outNbitsRegister

Example:

E(N-1) E(N-2) E(0)

S out std_logic_vector(N 1 downto 0));end Register;architecture structural of Register is

component DFFport (Clk : in std_logic;

E i td l i

DFF DFF DFF

E : in std_logic;S : out std_logic);

end component;variable I : integer;

begin

Clk S(N-1) S(N-2) S(0)GenReg: for I in N-1 downto 0 generate

Reg: DFF port map(Clk, E(I), S(I));end generate;

end structural;61

VHDL Sentences (small selection) .44ConcurrentSentences:Assert,Procedurecalland Functioncall Sameusageandbehaviourastheequivalentsequentialones,butintheconcurrentworld.

[label:] assert [report ]

ConcurrentProcedurecallisjustlikeaprocesswithprocedureparametersinthesensitivitylist

[report ][severity (note | warning | error |failure);

list.

F ti ll ld b b dd d i i i id t t t t

[label:] [()];

Check_Timing(min_time, max_time, clk, sig_to_test, testOK);

Functioncallcouldbeembeddedinanyexpressioninsideaconcurrentstatement.

function Check_Timing(min_time, max_time, clk, sig_to_test) returns boolean;

assert Check_Timing(min_time, max_time, clk, sig_to_test) report Timing errorseverity (warning); 62

VHDL Modelling, Simulation & Synthesis .44entity Exercise is end;architecture Code of Exercise issignal a b : std logic vector(3 downto 0);signal a, b : std_logic_vector(3 downto 0);signal opcode : (add, sub);signal z : std_logic_vector(3 downto 0);Begin

FuT: process (a, b, opcode); Function under testvariable x, y : std_logic_vector(3 downto 0);variable s : std_logic; signal sign : std_logic;beginif a >= b then x := a; y := b; s := 0;

else x := b; y := a; s := 1;; y ; ;case opcode is

when add then z

VHDL Modelling, Simulation & Synthesis .44entity ParallelAdder is

generic (n : natural := 4);gport ( X, Y : in std_logic_vector(n-1 downto 0);


Cout : out std_logic);End ParallelAdder ;End ParallelAdder ;

achitecture Functional of ParallelAdder isBegin

process (X, Y, Cin);i bl d l i ( d t 0)variable C : std_logic_vector(n downto 0);

variable tmp : std_logic;variable I : integer;begin

C(0) := Cin;for I in 0 to n-1 loop


VHDL Modelling, Simulation & Synthesis .44entity ParallelAdder is

generic (n : natural := 4);gport ( X, Y : in std_logic_vector(n-1 downto 0);


Cout : out std_logic);End ParallelAdder ;End ParallelAdder ;

achitecture Functional of ParallelAdder isBegin

process (X, Y, Cin);i bl d l i ( d t 0)

Logic Simulation

variable C : std_logic_vector(n downto 0);variable tmp : std_logic;variable I : integer;begin

C(0) := Cin; Coutfor I in 0 to n-1 loop


VHDL Summary (part-III) 4 .4Sessionsummary VHDLconcurrentsentences(insideanarchitecture,blockorentity)

Selectedsentences: Process Components Assert

VHDLmodelling,simulation&synthesis:basicconceptsandflows

VHDL E l b d l i

signalassignments(uncond &cond.) Generate Functions&Procedures

VHDLExamplesbasedlearning

ThisendsourshortintroductiontoVHDLlanguageforitsusageinthecurrentg g gDigitalSystemsCourse

67

4Basics on VHDL lexical & syntax .2VHDLDataTypes

TheVHDLisastronglytypedlanguage Adatatypedefinesasetoffixedandstaticvalues Anylanguageobjectbelongstoaspecificdatatype Objectvaluesshallbelongtorelateddatatype Newdatatypescouldbeuserdefinedtype Result is real;

type mark is range 10.0 downto 0.0;......type Price is integer;type Month is range 1 to 12;...type Cardinal is (North, South, East, West);t C dK i (N S E W)type CardKeys is (N, S, E, W);type Mixed is (N, South, East, W);...variable Direction : Cardinal := West;variable Var : Mixed;Signal Key : CardKeys := N;...Var := N; -- Var & Key cannot be assigned to each other asKey

VHDL Design Units .2CONFIGURATION

4 Foreachcomponentinaspecificarchitectureselectsthemodule(entity+

architecturetobemappedonit Example:

architecture structural of MUX21 issignal Ctrl_n, N1, N2 : bit;component INVport( Y : in bit;

Z : out bit);Z : out bit);end component;component AND2port( X, Y : in bit;

Z : out bit);end component;

configuration mux21_cfg of MUX21 isfor structural

for U0 : INV

TTLcomponent OR2port( X, Y : in bit;

Z : out bit);end component;

beginU0: INV port map (Ctrl, Ctr n);

for U0 : INV use entity CMOS.INV(Funct);

for all : AND2use entity TTL.AND2(Funct);

for U3 : OR2i 2

CMOSp p ( , _ );

U1: AND2 port map (Ctrl_n, A, N1);U2: AND2 port map (Ctrl, B, N2);U3: OR2 port map (N1, N2, Z);

end structural;

use entity CMOS.OR2(Funct);end for;

end mux21_cfg;70

VHDL Sentences (small selection) .3SequentialSentences:VariableAssignment

4 Immediate replacementofvariablevalue. Syntax:

[label:] := ;

Nonequivalentsequences:A := B;B := A;

B := A;A := B;

Examples:Var := 0;V t 00011100Vector := 00011100;string := Message is: ;A := B;B := my_function(3,databus)C := my_function(4,adrbus) + A;

71

VHDL Sentences (small selection) .3SequentialSentences:Wait Indicates the point where a process execution shall be suspended as well as the

4 Indicatesthepointwhereaprocessexecutionshallbesuspended,aswellasthe

conditionsforitsreactivation.Morethanonewaitsentenceperprocessispossible. Syntax:

[label:] wait [on {, ...}] processb i

Basicexamples:

[until ][for ];

beginClock

VHDL Sentences (small selection) .3SequentialSentences:Ifthenelseendif;

4 SelectsthegroupofsentencestoexecutedependingonaBooleancondition. Syntax:

[label:] if then

processbegin

Buffer Triestate[label:] if then

{elsif then

VHDL Sentences (small selection) .3SequentialSentences:If&Case

entity LatMux is

4 AnotherexampletocombineIf&Case

sentencesinasingleProcess.

entity LatMux isport(

Load : in bit;A, B, C, D : in bit;Ctrl : in bit_vector(0 to 1);Y : out bit);

end LatMux;

architecture OneProc of LatMux isbegin

A

LatMux

gprocess (Load, Ctrl, A, B, C, D);begin

if Load=0 thencase Ctrl is

when 00 => Y Y < A;when 01 => Y Y Y

VHDL Sentences (small selection) .3SequentialSentences:Loop

4 Sequentialsentencesintheloopregionarerepeatedforanumberoftimes. Typesofloops:while,forandwithoutiterationscontrol(infiniteloop). Syntax: [label:] [while | for ] [ abe :] [ e boo ea _co d t o | o epet t o _co t o ]

loop}

end loop [label];

Examples:countermod16

processbegin

Processvar I : integer;begin

Cont

VHDL Sentences (small selection) .3SequentialSentences:Loop,Exit&Nextexample(countermodule16)

4

entity Counter16 isport(

Clock, Rst : in bit;Count : out natural);

Countermodule16withasynchronousreset

entity Counter16 isport(

Clock, Rst : in bit;Count : out natural);

Countermodule16whichavoidsvalue8

end Counter16;

architecture functional of Counter16 isvariable C : natural;begin

Cou t : out atu a );end Counter16;

architecture functional of Counter16 isvariable C : natural;variable I : integer;begin

processbegin

C := 0;loop

it til ((Cl k t d Cl k 1)

variable I : integer;begin

processbegin

C := 0;wait until ((Clockevent and Clock = 1)

or Rst = 1);exit when Rst = 1;C := (C + 1) mod 16;

end loop;

for I in 0 to 15 loopnext when I=8;C := I;wait until Clock=1;

end loop;end process;Count

VHDL Sentences (small selection) .4ConcurrentSentences:Generate

4 Example: entity ShiftReg is

generic (N: positive);port( Clk, SIn : in bit ;

SOut : out bit);end ShiftReg;

NbitsShift register

X(0) X(N 2)end ShiftReg;architecture structural of ShiftReg is

component DFFport (Clk, E : in bit;

S : out bit);

SIn SOutX(0) X(N-2)

DFF DFF DFF

end component;signal X : bit_vector(0 to N-2);variable I : integer;

beginGenShReg: for I in 0 to N-1 generate

Clk

g gG1 : if (I=0) generate

CIzq: DFF port map(Clk, SIn, X(I)); end generate;G2 : if (I>0) and (I

VHDL Sentences (small selection) .4ConcurrentSentences:Generate Example: entity ParallelAdder is N bits Parallel Adder

4Example: y

generic (n : natural),port ( X, Y : in bit_vector(n-1 downto 0);

Cin : in bit;Z : out bit_vector(n-1 downto 0);Cout : out bit);

NbitsParallelAdder

Cout : out bit);End ParallelAdder;architecture structural of parallelAdder iscomponent FA

port ( A, B, Ci : in bit;S C t bit) C0=Ci

Cout=CnX0 Y0Xn-2 Yn-2Xn-1 Yn-1

CCS, Co : out bit);end component;signal C : bit_vector(n downto 0);variable I : integer;begin

C0 Cin

n

FA FA FA

C1Cn-1

ZZ ZGenShReg: for I in 0 to N-1 generateG1 : if (I=0) generate

LSB: FA port map(X(I), Y(I), Cin, Z(I), C(I+1)); end generate;G2 : if (I>0) and (I

VHDL Sentences (small selection) .4ConcurrentSentences:Generate Example:

4Example: entity ParallelAdder is

generic (n : natural),port ( X, Y : in bit_vector(n-1 downto 0);

Cin : in bit;Z : out bit vector(n-1 downto 0);

NbitsParallelAdder

Z : out bit_vector(n 1 downto 0);Cout : out bit);

End ParallelAdder;

architecture structural of ParallelAdder iscomponent FA X YX YX Ycomponent FA

port ( A, B, Ci : in bit;S, Co : out bit);

end component;signal C : bit_vector(n downto 0);

C0=CinCout=Cn

X0 Y0

FA FA FA

Xn-2 Yn-2Xn-1 Yn-1

C1Cn-1

variable I : integer;Begin

C(0)

VHDL Modelling, Simulation & Synthesis .44

VHDLSource code

VHDL Elaboration Sea of processesVHDL

SimulatorLibrariesVHDL Analyser

VHDL Simulation .4VHDLEventDrivenSimulationCycle

4y

Which processes shall be resumed?

Updating Signals & Time

Processes Execution

Update signals drivers

shall be resumed?

y/ny/n y/n

y/nInitializeSignals

?

Signals drivers

T. . .

SignalsDrivers

roce

ss-1

roce

ss-2

roce

ss-n

Initialization

dela

y

T

STOPWait till all resumed

P P P

0 1 3 4 5

dTime

Wait till all resumed processes are stopped

81

VHDL Summary (part-III) 4 .4Sessionsummary VHDLconcurrentsentences(insideanarchitecture,blockorentity)

Selectedsentences: signalassignments Process Generate

VHDLmodelling,simulation&synthesis:basicconceptsandflows

VHDL t d i i l ti f

Conditionedsignalassignments Components Assert,Functions&Procedures

VHDLeventdrivensimulationofprocessesoceans

Simulationcycle

delayversussimulationtime

VHDLExamplesbasedlearning

ThisendsourshortintroductiontoVHDLlanguageforitsusageinthecurrentDigitalSystemsCourse 82

Semana 4 - Lecciones

Documents

Transcript of Semana 4 - Lecciones