UNIVERSIDAD AUTONOMA METROPOLITANA UNIDAD …148.206.53.84/tesiuami/UAM3555.pdf · 2004-03-08 ·...

UNIVERSIDAD AUTONOMA METROPOLITANA

UNIDAD IZTAPALAPA

CIENCIAS BASICAS E INGENIERIA

PROYECTO DE INGENIERIA ELECTRONICA I y 11.

ALUMNA:EMMA BRISEYDA YAÑEZ MEDINA.

MATRICULA. 94218932.

ASES0R:OMAR AMIN ABDEL RAHAMAN.

Trimestre 00-1. MCxic0.D.F. I2 de abrir 2000.

ANALISIS Y SINTESIS DE VOZ

Realización alterna para generación de formas de onda.

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INDICE

PREFACIO .................... 4

INTRODUCCION ......... 5

IMPLEMENTACION DESARROLLO ........... 16

CONCLUSIONES ........ 22

REFERENCIAS ........... 23

. . * i

r ;

3

PREFACIO

El objetivo principal de este proyecto, es presentar el desarrollo de un codificador para la compresión de las sefiales de voz, el enfoque que se le ha dado es a partir del algoritmo CORDIC, el cual ha sido realizado dentro de un circuito integrado FPGA (Field Programmable Gate Array) usando el dispositivo XS30 de Xilinx.

En la primera parte de este trabajo, se presenta la información en la que se basa el diseño y un panorama general del análisis de voz a partir del esquema de un sistema de comunicaciones. Más adelante se describe el desarroIlo del prototipo con una serie de tablas y diagramas que ayudan a la compresión del diseño.

En la última parte se presentan las hojas de especificaciones que han resultado del mapa, la colocación de los dispositivos y la optimización de estos dentro del circuito; se muestra además el diagrama interno del mismo.

El propósito es proporcionar las bases para obtener un circuito integrado que pueda ser utilizado como cualquier otro circuito que se encuentre actualmente de manera comercial, el cual permita su uso en la compresión de voz, así como en otro tipo de aplicaciones.

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INTRODUCCION

Un sistema de comunicación está formado en general por varios bloques, que son el codificador y el modulador, en la etapa de transmisión; el canal que es el medio fisico que une la fuente con el usuario, el demodulador y el decodificador en el receptor.

Modulador Canal Demodulador Decodificador

U Usuario

El codificador de canal reduce el impacto del ruido del canal, insertando redundancia en los datos que han sido codificados.

f \ f \ Codificador

de canal b de fbente Codificador

Los códigos de canal, insertan redundancia en los datos transmitidos, para que el receptor pueda detectar y posiblemente corregir, los errores que ocurren durante la transmisión. Una de las técnicas que se utilizan es el código Hamming, que corrige un error cada 7 bits y los códigos BCH y Reed- Solomon, que se consideran de los más poderosos en la familia de los códigos de bloque.

El modulador mapea la información, en señales que pueden ser eficientemente transmitidas, sobre el canal de comunicación y se puede escoger, entre una variedad de métodos para modulación, dependiendo del objetivo que se pretenda alcanzar.

El canal físico, atenúa la señal transmitida e introduce los efectos de ruido, interferencia, propagación y distorsión. La atenuación es generalmente causada por la absorción de energía y dispersión en el medio de propagación.

La función del receptor, es efectuar las operaciones inversas a las del transmisor, para recuperar la información con la menor cantidad de errores posible. El demodulador, recupera los datos de la señal recibida y los lleva al decodificador.

El deco&ficador, se divide en dos bloques, el decodificador de fuente y el decodificador de canal, que realizan las operaciones inversas a las del codificador, y finalmente envía la información al usuario.

Decodificador Decodificador de canal de fuente 1

El modelo de un sistema de comunicación muestra la relación del codificador y decodificador con el resto del sistema, y de ahí que sea el punto de partida para el estudio del análisis de voz, que ha tenido un papel esencial en la expansión de las comunicaciones, debido a la gran cantidad de aplicaciones que de é1 se derivan.

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Propiedades básicas de la voz

La voz es producida cuando el aire es inyectado desde los pulmones, a través de las cuerdas vocales y a lo largo del tracto vocal. El tracto vocal se extiende desde la abertura de las cuerdas vocales (glotis) a la boca, y en promedio es de 17cm de largo.

La salida de las cuerdas vocales es semejante a una excitación de pulsos, la cual es rica en armónicos. Esta s ek l es modelada por la garganta, boca y nariz. La variedad de armónicos se incrementan o decrementan relativamente uno a otro para formar los diferentes sonidos. Las frecuencias resonantes del sistema vocal son llamadas formantes.

Una parte importante en el análisis de voz, es el modelado del tracto vocal como un filtro, como la forma de éste varía relativamente despacio, la función de transferencia del filtro, no necesita ser actualizada con mucha frecuencia (20ms más o menos).

El filtro del tracto vocal es excitado por el aire, dependiendo del modo de excitación, los sonidos pueden dividirse en tres clases:

Sonidos sonoros

Estos son producidos, cuando las cuerdas vocales vibran abriendo y cerrando, interrumpiendo así, el flujo de aire de los pulmones al tracto vocal, produciendo pulsos casi periódicos de aire. El ritmo de la abertura y el cerrado da el tono del sonido (pitch). Esto puede ser ajustado, variando la forma de la tensión en las cuerdas vocales, y la presión del aire a través de ellas. Este tipo de sonidos muestran un alto grado de periodicidad, en el período del tono, generalmente entre 2 y 20ms.

El pitch promedio para la voz masculina se encuentra alrededor de 130Hz, la voz femenina es aproximadamente un octavo más alta.

Sonidos sordos

Resultan cuando la excitación es turbulencia de tipo ruido, producida por la inyección de aire a altas velocidades, a través de una constricción en el tracto vocal mientras el glotis está totalmente abierto. Estos sonidos tienen periodicidad, de términos largos.

Sonidos explosivos

Resultan cuando se cierra completamente el tracto vocal, y la presión de aire se reúne detrás de este cierre y se libera de repente.

7

Algunos sonidos no caen dentro de esta clasificación, porque son una mezcla de ellos. Por ejemplo: los sonidos fricativos, que resultan cuando se presentan ambos, vibración de las cuerdas vocales y constricción del tracto vocal.

Aunque hay muchos sonidos, que pueden producirse, la forma del tracto vocal y su modo de excitación cambian relativamente despacio, así que la voz puede considerarse casi estacionaria, sobre períodos cortos de tiempo (del orden de 20ms).

Las señales de voz, muestran alto grado de predicción, debido a las vibraciones casi periódicas de las cuerdas vocales y también debido a la resonancia del tracto vocal. La codificación de voz intenta explotar esta capacidad de predicción, para reducir el índice de datos necesarios para transmisión de alta calidad. I f

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Los codificadores de voz son dispositivos de codificación simplificada, los cuales 1- r extraen de manera eficiente, los componentes significativos en una señal de voz, explotando la redundancia de la voz, para alcanzar bajas tasas de transmisión de bits. La voz consta básicamente de cuatro formantes, y el codificador de voz analiza la señal de entrada, para encontrar como la posición y las magnitudes, de esos formantes varian con el

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Criterios para la selección de codificación de voz

Los criterios que generalmente deben tomarse en cuenta, antes de escoger una técnica para la codificación de voz, son los siguientes:

Tasa de bit

0 Calidad de voz

Retardo

Complejidad

8

Tasa de bit

Los algoritmos para codificación de voz de alta calidad, están disponibles desde 6.3 Kbps. Muchos algoritmos, resultan en una tasa de compresión la cual es un múltiplo de 64 Kbps para facilitar una eficiente multiplexión.

Calidad de voz

MOS (Mean Opinion Score) es un sistema común de estimación donde los oyentes califican la calidad de voz en una escala de 1.0 a 5.0. Una puntuación MOS de alrededor de 4.0 implica alta calidad. Los codificadores paramétricos generalmente alcanzan alta calidad.

Retardo

Casi todos los codficadores de voz añaden retardo, ya que las técnicas de compresión más eficientes resultan cuando operan en bloques de datos. Los algoritmos típicos, más los retardos de procesamiento son de 5 a 45ms en cada dirección.

I

Complejidad

Millones de instrucciones por segundo (MIPS) y los requerimientos de memoria tienen un fuerte impacto en el costo final del sistema. Típicamente varían de 5 a 50 MIPS dependiendo del algoritmo y el objetivo del procesador.

Técnicas de codificación paramétrica

Las técnicas paramétricas generan parámetros, que modelan matemáticamente la sefial de entrada. El resultado es una señal que suena como la original, pero que no necesariamente es similar en forma de onda.

La mayoría de las técnicas de compresión de voz, son técnicas paramétricas, ya que una tasa de bit más baja (razón de compresión alta) con una calidad razonable, es más importante que muy alta calidad.

9

En la tabla siguiente se mencionan algunas de las técnicas de codificación y sus características.

Técnicas de Estándar Codificación Ley A leyp PCM 6.711

ADPCM I 6.726

CS-ACELP 6.729

LPC USFS-1015

CELP USFS-1016

VSELP IS-54B/

ACELP IS-641

anexo A

IS-136

WE-LTP GSM rango Completo

VSELP GSM medio rango

ACELP GSM rango de incremento completo

Tasa de duplex mseg MIPS MOS compresión Retardo full- Complejidad Calidad

64Kbps 4.3 O

7.5 20-45 4.0 16Kbps O 10-16 32Kbps Kbps

4.1 @ 16/24/32/40 O

6.4Kbps /

30 20-28 4.0 8Kbps 100 22-28 6.4Kbps 5.3Kbps

3.9@

I I I

8Kbps 65 6-12 2.3 2.4Kbps 30 10 3.9

4.8Kbps 90 13-25 3.2

7.95Kbps 60 13-18 4.0 7.4Kbps 60 20-25 3.5

13Kbps

60 21-30 3.5 5.6Kbps

60 3-6 3.5

12.2Kbps 60 18-25 4.0

10

Entre las técnicas de codificación de voz, una de las más difundidas es LPC, por la baja tasa de bits que proporciona, es por eso importante mencionar brevemente en que consiste.

LPC (Linear Predictive Coder)

El codificador de voz LPC es usualmente implementado como una cascada de filtros de predicción lineal de errores, que eliminan de la señal de voz los componentes que pueden predecir de su historia previa por el modelado del tracto vocal como un filtro de todo polo.

En el codificador de voz LPC, el analizador y el codificador normalmente procesan la señal en tramas de 20ms y subsecuentemente transmiten la información espectral por medio de los coeficientes del filtro. El error residual de salida de la operación de estimación paramétrica no es transmitido. La señal de error es usada para proporcionar una estimación del nivel de potencia de entrada, el cual es enviado con la información de tono (pitch) y la información de si la entrada es sorda o sonora. El decodificador y el sintetizador aplican los coeficientes recibidos a un filtro, el cual es excitado con impulsos en la frecuencia del pitch si es sonoro, o por ruido blanco si es sordo. La amplitud de la excitación es controlada por la información estimada de la potencia de entrada. Esta excitación con una señal sintética reduce la tasa de bits de transmisión, pero también reduce la calidad de la voz.

Con retardos en el tracto vocal de lms y rango de muestre0 de voz de 8 a lOkHz, el número de estados que se predxen es normalmente de 8 a12; 10 es el número adoptado como el estándar para codificador de voz LPC-10, que transmite en una tasa de 2.4kbps y alcanza un MOS de aproximadamente 2.

La puntuación MOS es baja debido a la excitación con ruido o información de pitch regenerada, esto ocasiona que se pierdan todos los sonidos de fondo y entonces la voz tenga un sonido metálico.

LPC h e diseñado para aplicaciones de segundad militar donde la alta calidad de voz no es tan importante como una baja tasa de bits. Además es usado para cientos de aplicaciones de sistemas comerciales de voz, como los juguetes.

Tren de impulsos (sonido sonoro)

tttttt Predictor

De orden 10 b Lineal

1 1

CORDIC

En el procesamiento dlgital de sefíales, el uso de algoritmos eficientes de hardware es una solución cuando se desea mayor velocidad de procesamiento, esta clase de algoritmos están basados en soluciones iterativas para funciones trigonométricas y otras hc iones trascendentales que necesitan solamente sumas y desplazamientos para realizarse.

El algoritmo llamado CORDIC Coordinate Rotation DIgital Computer, es un método para realizar las funciones trigonométricas; este método es usado típicamente cuando estas funciones necesitan ser implementadas directamente en hardware.

Los algoritmos trigonométricos CORDIC fueron originalmente desarrollados en 1950, como una solución digital para problemas de navegación en tiempo real. El trabajo original es acreditado a Jack E.Volder en 1959 y después se hicieron extensiones del algoritmo basados en trabajos de John Walter. Se ha utilizado en diversas aplicaciones incluyendo el coprocesador matemático 8087, la calculadora HP-35, procesadores de sefiales de radar. Además ha sido planteado para la solución de las transformadas discreta de Fourier, Hartley, transformada Z, filtrado y solución de sistemas lineales.

Todas las funciones trigonométricas están basadas en rotaciones de vectores. La rotación de vectores también puede usarse para conversión de polar a rectangular y de rectangular a polar, etc. El algoritmo CORDIC, proporciona un método iterativo que trabaja por la rotación de vectores a través de ángulos constantes, hasta que el ángulo es reducido a cero usando solo sumas y desplazamientos.

El algoritmo se deriva de la transformada general de rotación:

x'= xcos6- ysen6 y'= ycos6 + xsen6

Podemos reescribir lo anterior de manera que podamos tener la tangente del ángulo:

x'lcos6 = x- y.tant9

y'lcos6 = y+x. tanQ

12

Ahora si restringimos los ángulos de rotación de tal manera que:

tan (O) = +2"

la multiplicación por el término tangente es reducida a una simple operación de desplazamiento. Para tomar la decisión en cada iteración i, de la dirección para rotar, el término cos(6i) se considera una constante, porque ( cos(6i) = cos(&)). Entonces la expresión queda como sigue:

donde: di = +1

i=O

n = número de bits

El resultado de Ki es aproximadamente 0.6073, puesto que el número de iteraciones va al infinito.

El ángulo de una rotación compuesta está definido únicamente por la secuencia de las direcciones de las rotaciones elementales. Esa secuencia puede ser representada por un vector de decisión. El conjunto de todos los posibles vectores de decisión es un sistema de medición angular basado en arcotangentes binarios. Para convertir este sistema angular en cualquier otro, se puede usar un sumador-restador, que acumule los ángulos de rotación elementales, en cada iteración. Los ángulos se expresan en cualquier unidad de medtción; estos valores angulares pueden proporcionarse directamente de una memoria donde se encuentren almacenados. El acumulador de ángulos suma una tercera ecuación al algoritmo CORDIC:

z,+, = zi -d i -tan" (2-j)

La rotación del CORDIC, es normalmente operada de dos modos. El primero llamado rotación, en el que se rota el vector de entrada por un ángulo especificado (dado como un argumento). El segundo llamado vectorización, que rota el vector de entrada por el eje x, mientras registra el ángulo requerido para hacer la rotación.

13

Para el modo de rotación, la decisión de rotación en cada iteración está basada en el signo del ángulo residual después de cada paso, las ecuaciones CORDIC, se expresan entonces como sigue:

',+I =X, - y i * d i *2" yi+l = yi + xi * d i 2- i

zi+l = zi -d i . t~~n"(2")

donde:

di = -1 si Zi < O, +1 en otro caso. es decir:

d, = ~ g n z ,

En el modo de rotación, la operación CORDIC puede simultáneamente, calcular al seno y el coseno del ángulo de entrada. Tomando la componente 'y' del vector de entrada como cero, entonces las ecuaciones se reducen a:

x, = A, 'X, cosz,

y , = A, x, sen z,

haciendo:

X, =1/A,

la rotación produce, el seno y el coseno del ángulo del argumento de 20.

Conversión de polar a rectangular

La transformación del plano polar al cartesiano, está definido por:

x = rcos8 y = rsen8

Con el modo de rotación, se selecciona a Xo = magnitud polar, Zo = fase polar, y Yo= O. El vector resultante representa la entrada polar transformada al plano cartesiano.

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FPGA

FPGA (Field Programmable Gate Array) es un tipo de dispositivo programable. Los dispositivos programables son una clase de circuitos integrados de propósito general que se configuran para una variedad de aplicaciones. Hay cuatro categorías de FPGAs disponibles comercialmente: arreglos simétricos, basados en filas, PLD (Programmable Logic Device) jerárquico, y mar de compuertas. En cada uno de estos las interconexiones y la manera en como se programan varía. Actualmente hay cuatro tecnologías en uso: celdas RAM estáticas, anti-fusión, transistores EPROM, y transistores EEPROM.

El FPGA tiene tres principales elementos configurables: bloques lógicos configurables (CLBs), bloques entraddsalida, e interconexiones. Los CLBs proveen los elementos funcionales para construir la lógica del usuario. Los IOBs proporcionan la interface entre las patas del empaque y las líneas de señal interna. Los recursos de interconexión programable proporcionan trayectorias de encaminamiento para conectar las entradas y salidas de los CLBs y los IOBs en las redes apropiadas. La configuración personalizada es establecida por la programación interna de las celdas de memoria estática que determinan las funciones lógicas y las conexiones implementadas en el FPGA. Todas las conexiones internas están compuestas de segmentos de metal con puntos de conmutación programable para implementar las rutas deseadas. Una abundancia de diferentes recursos de encaminamiento es proporcionada para alcanzar un eficiente encaminamiento automático. Se pueden distinguir tres maneras de interconexiones, por la longitud relativa de sus segmentos: líneas de longitud sencilla, líneas de longtud doble, y líneas largas. La secuencia del diseño de un FPGA, es como sigue:

Inicio del diseño En esta etapa el circuito digital es creado con un editor de diseño digital esquemático,o

un lenguaje de descripción de hardware (HDL). El programa de entrada esquemático utiliza símbolos gráficos de la circuiteria. Implementaci6n del diseíio (mapa)

El circuito producido en la etapa anterior es convertido en el archivo de flujo de bits el cual configura al FPGA. El primer paso mapea el diseño en los recursos del FPGA; el segundo paso coloca los bloques creados en el mapa en las locaciones especificas del FPGA. El tercer paso encamina las trayectorias de interconexión entre los bloques lógicos. La salida es un archivo de arreglo de celdas lógicas (LCA), para el FPGA en particular. Este archivo se convierte en un archivo de flujo de bits para la configuración del FPGA. Verificación del diseño -simulación

de entrada. Configuración FPGA

La configuración es el proceso en el cual el circuito(archivo de flujo de bits) es descargado en el FPGA. Los FPGAs pueden configurarse de diferentes formas: por una PROM, escribiendo los datos de la configuración en el FPGA (modo esclavo y periférico) o bien el archivo de flujo de bits puede convertirse en una función de lenguaje de alto nivel.

En esta parte se hacen las pruebas de lógica de diseño y de tiempo usando estímulos

IMPLEMENTACION

DESARROLLO

El diagrama general que se ha propuesto para el análisis de voz, se muestra en la siguiente figura.

cos 3t r

1 3 t

I FPB b U

Donde f(t) es la señal de voz, y las K’s representan los coeficientes obtenidos en la salida, además podemos ver que las funciones seno y coseno son la parte fundamental para el desarrollo de este sistema.

16

Para obtener las funciones seno y coseno, se ha implementado el CORDIC, de acuerdo a las ecuaciones que se mencionan en la introducción.

Las ecuaciones trigonométricas planteadas en el CORDIC, se desarrollaron por medio de dos sumadores-restadores, para cada una de las entradas, X,Y,Z, puesto que está diseñado para ocho bits.

Los ángulos de las tangentes se calcularon por medio de un programa en lenguaje C, y se almacenaron en binario, directamente en las entradas de los sumadores-restadores, de la ecuaci6n Z, de esta manera se vuelve innecesario el uso de una memoria ROM, y se simplifica el circuito.

Se observa que en las últimas iteraciones, los valores de los ángulos de las tangentes, son tan pequefios que su valor pierde utilidad, entonces es necesario multiplicar, cada valor por 2, hasta que su valor resulta aceptable. Estos valores, además, han sido cuantizados a 8 bits antes de ser aplicados a las entradas de los sumadores-restadores, al igual que los valores iniciales para X y Y.

Los valores del ángulo de la tangente y sus correspondientes valores cuantizados en signo magnitud, se presentan en la siguiente tabla:

tan" 2" I O I 44.9999999999970370 I 80 1 I 1 I 26.5650511770762421 1 4C I

2 3

28 14.0362434679255550 14 7.1250163489013287 1 1 1

0.8951737102110153 I 7 I 0.4476141708605236 I O1 I

17

Los valores siguientes, son los que resultan de las ocho iteraciones, para calcular el seno y el coseno, tomando como ángulo 30°, estos valores se utilizaron en el desarrollo del circuito para hacer pruebas de su funcionamiento, aunque el circuito que resulta finalmente está implementado de manera que en sus entradas, se puedan introducir valores para cualquier ángulo.

Los valores iniciales se calculan previamente, es decir el producto Ki, se obtiene como se menciona en los conceptos teóricos y Y se considera cero, para este caso.

i

4E 0.60725911231 4E 0.60725911231 1 O O 4E 0.60725911231 O

Y X I

2

41 0.510651392813 6E 0.85961041029 6 3E 0.48331657864 70 0.87471405337 5 37 0.42697906334 73 0.90140024483 4 44 0.53135172327 6B 0.83498127942 3 27 0.30362955615 75 0.91088668465

I 7 10.86758933830 I 70 I 0.497219980152 I 40 I

Para realizar los productos necesarios en las ecuaciones X y Y solamente es necesario hacer desplazamientos en las entradas de X, cuando se tiene a Y como salida y viceversa. Esta es una de las ventajas del CORDIC sobre otros métodos, porque al utilizar múltiplos de dos en lugar de necesitar multiplicadores para esta operación, se requiere simplemente de un desplazamiento.

Como el CORDIC ha sido disefiado para ocho bits, se necesitan siete módulos funcionales, cada uno se ha implementado de la manera descrita anteriormente; no es necesario describir en detalle cada uno, pues las características mencionadas cumplen para todos los módulos, sin embargo es importante mencionar que los desplazamientos se realizan a partir del módulo uno para X y Y y desde el módulo dos para el ángulo de la tangente, que es cuando se vuelve necesario; de las ecuaciones se observa que el s g n z, es quien determina si se suma o se resta en cada iteración, esto se obtiene en el circuito con un inversor a la salida del ADD de 2, para el caso de X y para Y el signo es el mismo que el de 2. En el módulo cero no es necesario, porque los signos se conocen de las condiciones iniciales y como se sabe que el valor de Cin es opuesto al de ADD, conectándolos entre sí tendremos, suma o resta según el caso..

A continuación se muestra el diagrama general y los siete módulos jerárquicos, es decir donde se puede ver de manera interna cada uno de ellos

18

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rq

rwq

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" - 1, :_I

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La información que se presenta en las páginas siguientes, es la que ha sido proporcionada por los reportes de cada una de las etapas que se siguen para el desarrollo del circuito integrado, a partir del esquemático.

Reporte del mapeo.

Información del diseño

Son las caractensticas del circuito integrado; el dispositivo utilizado en este diseño es el XS30, en un empaque vq100, con velocidad -3, usando la versión Spartan.

Resumen del diseño f

Aquí se indica el número de errores, que existen después de correr el diseño, en este caso cero, pero se presentaron 78 advertencias. También aparece el número de CLBs (Configurable Logic Blocks), se ocupa el 30%, el 62% de los IOBs.

El total de compuertas es 2 144 y las compuertas adicionales JTAG para los IOBs son 2304.

. .

...

Contenido: Sección 1. Errores. Sección 2. Advertencias. Sección 3. Atributos del diseño. Sección 4. Resumen de lógica removida. Sección 5. Lógica removida. Sección 6 . Lógica adicionada. Sección 7 . Lógica expandda. Sección 8. Referencia comparativa de las señales. Sección 9. Referencia comparativa de símbolos. Sección 10. Propiedades de los IOB. Sección 1 1. RPM’s. Sección 12. Reporte guía.

Advertencias

En este diseño las advertencias aparecieron debido a que no se interpretaban de manera correcta los nombres en los buses, además en cada uno de los módulos y en las entradas del circuito había confusión con respecto a los PAD y los IBUF, lo mismo sucedía en las salidas.

19

Xilinx Mapping Report File for Design "emma" Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved.

Design Information

Command Line : map -p xcs30-3-vq1OO -o map.ncd emma.ngd emma.pcf Target Device : xs30 Target Package : vql00 Target Speed : -3 I

Mapper Version : spartan -- M1.5.19 Mapped Date : Sun Mar 26 15:44:51 2000

"""""""""

Design Summary """""""

Number of errors: O Number of warnings: 78 Number of CLBs: 179 out of 576 31%

CLB Flip Flops: O 4 input LUTs: 214 3 input LUTs: 3

IOB Flops: O IOB Latches: O

Number of RPM macros: 42

Number of bonded IOBs: 48 out of 77 62%

Total equivalent gate count for design: 2144 Additional JTAG gate count for IOBs: 2304

Table of Contents

Section 1 - Errors Section 2 - Warnings Section 3 - Design Attributes Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - Added Logic Section 7 - Expanded Logic Section 8 - Signal Cross-Reference Section 9 - Symbol Cross-Reference Section 10 - IOB Properties Section 11 - RPMs Section 12 - Guide Report

_""""""""

Section 1 - Errors """""""""

Section 2 - Warnings

WARNING:baste:24 - All of the external outputs in this design are using

outputs can be

original

""""""""""

slew-rate-limited output drivers. The delay on speed critical

dramatically reduced by designating them as fast outputs in the

design. Please see your vendor interface documentation for specific information on how to do this within your design-entry tool. Note: You should be careful not to designate too many outputs which

together as fast, because this can cause excessive ground bounce.

information on this subject, please refer to the IOB switching

switch

For more

characteristic

guidelines for the device you are using in the Programmable Logic Data Book. WARNING:x4kma:lll - All the logic for FMAP symbol "H8/$16/$11301f1 (output

being

see if

WARNING:x4kma:lll - All the logic for FMAP symbol "H8/$13/$11301rr

signal=HE/$IG/CO) has been removed! This may be caused by key logic

trimmed. Please consult the Removed Logic section of this report to

this is the case.

(output signal=H8/$13/CO) has been removed! This may be caused by key logic

trimmed. Please consult the Removed Logic seccion of this report to

this is the case.

being

see if

WARNING:x4kma:lll - All the logic for FMAP symbol "H8/$118/$11293'1 (output

signal=H8/$118/OFL) has been removed! This may be caused by key


this is the case.

logic being

see if

WARNING:x4kma:lll - All the logic for FMAP symbol "H8/$116/$11293' (output

signal=HE/$IlG/OFL) has been removed! This may be caused by key


this is the case.

logic being

see if

WARNING:x4kma:lll - All the logic for FMAP symbol "H8/$113/$11293" (output

signal=H8/$113/0FL) has been removed! This may be caused by key


this is the case.

logic being

see if


signal=& A 39) has been removed! This may be caused by key logic


this is the case.

being

see if




this is the case.

being

see if




this is the case.

being

see if



being

see if

WARNING:x4kma:lll - All the logic for FMAP symbol "H8/$111/$11301'


this is the case.



this is the case.

being

see if


logic

report to


slgnal=H8/$Net00054 - ) has been removed! This may be caused by key

being trimmed. Please consult the Removed Logic section of this

see if this is the case.

(output

logic

report to

WARNING:x4kma:lll - All the logic for FMAP symbol "H6/$16/$1130111

signal=H8/$Net00055 - ) has been removed! This may be caused by key





this is the case.

being

see if


signal=H6/$13/CO) has been removed! This may be caused by key logic


this is the case.

being

see if

WARNING:x4kma:lll - All the logic for FMAP symbol "H6/$118/$11293'' (output



this is the case.

logic being

see if




this is the case.

logic being

see if


signal=HG/$I13/0FL) has been removed! This may be caused by key


this is the case.

logic being

see if

WARNING:x4kma:l?l - All the logic for FMAP symbol "H6/$113/$11206"

(output signal=& A 123) has been removed! This may be caused by key logic


this is the case.

being

see if


signal=&-A - 122) has been removed! This may be caused by key logic


this is the case.

being

see if

WARNIKG:x4kma:Ill - All th$ logic for FMAF spbG1 "HG/$I;3/$11204" (output



this is the case.

being

see if


signal=HG/$I11/CO) has been removed! This may be caused by key logic


this is the case.

being

see if


logic

report to

WARNING:x4kma:lll - All the logic for FMAP symbol "H6/$111/$11203"

signal=H6/$Net00054 ) has been removed! This may be caused by key

being trimmed. Please consult the Removed Logic sectior! of this


-

(output

logic signal=H6/$Net00055 ) has been removed! This may be caused by key

i-ing trimmed. Please consult the Removed Logic section of this

see if this is the'case.

-

rep:rr to




this is the case.

being

see if




this is the case.

being

see if


siqnal=H5/$118/0FL) has been removed! This may be caused by key

trimned. Please consult the Removed Logic section of this report to logic being

see if

this is the case. WARNING:x4kma:lll - All the logic for FMAP symbol "H5/$116/$11293" (output



this is the case.

logic being

see if


signal=HS/$I13/OFL) has been removed! This may be caused by key


this is the case.

logic being

see if

WARNING:x4kma:lll - All the logic for FMAP symbol "H5/$I13/$11206'f (output

signal=& A 9 8 ) has been removed! This may be caused by key logic

.trimmed. Please consult the Removed Logic section of this report to

this is the case.

being

see if

WARNING:x4kma:lll - All the logic for FMAP symbol "H5/$113/$11205'' (output

signal=&-A-97) has been removed! This may be caused by key logic


this is the case.

being

see if




this is the case.

being

see if





logic

report to

WARNING:x4kma:lll - All the logic for FMAP symbol "H5/$111/$11203'f

-

(output

logic

report to





-



this is the case.

being

see if


signal=H4/$13/CO) has been removed! This may be caused by key logic being

this is the case. WARNING:x4kma:lll - All the logic for FMAP symbol "H4/$118/$11293' (output



this is the case.

logic being

see if

WARNING:x4kma:lll - All the logic for FMAP symbol "H4/$116/$11293'f (output

lcqic being signal=H4/$116/OFL) has been removed! This may be caused by key


this is the case. see if


signal=H4/$113/OFL) has been removed! This may be caused by key logic being

trimmed. Please see if

this is the case WARNING:x4kma:lll -

signal=&-A - 73)

trimmed. Please

(output

being

see if

consult the Removed Logic section of this report to

All the logic for FMAP symbol "H4/$113/$11206f'

has been removed! This may be caused by key logic

consult the Removed Logic section of this report to

this is the case. WARNING:x4kma:lll - All the logic for FMAP symbol "H4/$111/$11301" (output



this is the case.

being

see if


logic

report to





-

(output signal=H4/$Net00055 - ) has been removed! This may be caused by key

logic being trimmed. Please consult the Removed Logic section of this

report to see if this is the case.


being

see if




this is the case.

(output



this is the case.

being

see if

WARNING:x4kma:ill - All the logic for FMAP symbol "H3/$118/$11293" i output

logic being

see if

WARNING:x4kma:lil - All the logic for FMAP symbol "H3/$116/$11293'



this is the case.

(output signal=H3/$116/0FL) has been removed! This may be caused by key


this is the case.

logic being

see if

WARNING:x4kma:ill - All the logic for FMAP symbol "H3/$113/$11293" (output



this is the case.

logic being

see if


signal=H3/$1il/CO) has been removed! This may be caused by key logic


this is the case.

being

see if

WARNING:x4kma:lll - A l l the logic for FMAP symbol "H3/$111/$11293" (output

signal=H3/$Net00054-) has been removed! This may be caused by key


see if this is the c.ase.

logic

report to


signal=H3/$Net00055 - ) has been removed! This may be caused by key



logic

report to


signal=HlO/$16/CO) has been removed! This may be caused by key logic


this is the case.

being

see if

WARNING:x4kma:lll - A l l the logic for FMAP symbol "H10/$13/$11301" (output

signal=HlO/$13/CO) has been removed! This may be caused by key logic


this is the case.

being

see if

WARNING:x4kma:lll - All the

signal=H10/$118/0FL) has

trimmed. Please consult

this is the case.

(output

logic being

see if

WARNING:x4kma:?ll - All the

signal=HlO/SIlG/OFL) has


this is the case.

(output

logic being

see if

WARNING:x4kma:lll - All the

signal=H10/$113/0FL) has


this is the case.

(output

logic being

see if

WARNING:x4kma:lll - All the (output

logic for FMAP symbol "H10/$118/$11293'

been removed! This may be caused by key

the Removed Logic section of this report to




logic for FMAP symbol "H10/$113/$11293''




signal=HlO/$Ill/CO) has been removed! This may be caused by key


this is the case.

logic being

see if


signal=Hl/$I8/CO) has been removed! This may be caused by key logic


this is the case.

being

see if


signal=Hl/$I4/CO) has been removed! This may be caused by key logic


this is the case.

being

see if




this is the case.

logic being

see if

WARNING:x4kma:lll - All the loGic for FMAP symbol "H1/$116/$11293" (output

signal=Hl/$IlG/OFL) has been removed! This may be caused by key


this is the case.

logic being

see if


signal=Hl/$I13/0FL) has been removed! This may be caused by key

trimmed. Please consult the Removed Logic section of this report to logic being

see if

WARNING:x4kma:lll - All the logic for FMAP symbol "H1/$11/$11301" this is the case.

(output signal=Hl/$Il/CO) has been removed! This may be caused by key logic


this is the case.

being

see if

WARNING:x4kma:340 - Signal " & A 142" on pin A0 of CY4 symbol "H3/$Ill/ $1197"

The

The

"

(output signal=H3/$111/C2) is not required by carry mode EXAMINE-CI.

signdl is being removeci. This carry component has been mode-reduced.

original carry mode was "ADDSUB-F-CI" .

WARNING:x4kma:340 - Signal "GLOBAL LOGIC1" on pin BO of CY4 symbol

mode

been

"H3/$111/$1197" (output signal=H3/$111/C2) is not required by carry

EXAMINE-CI. The signal is being removed. This carry component has

mode-reduced. The original carry mode was "ADDSUB-.F-CI".

WARNING:x4kma:340 - Signal 'I& A 140" on pin ADD of CY4 symbol "H3/ $Ill/$1197"

The

"

(Output signal=H3/$111/C2) is not required by carry mode EXAMINE-CI.

signal is being removed. This carry component has been mode-reduced.

original carry mode was "ADDSUB-F-CI" . The

WARNING:x4kma:340 - Signal " & A 43" on pin A0 of CY4 symbol "H4/$Ill/ $1197"

"

(output signal=H4/$111IC2) is not required by.carry mode EXAMINE-CI The



WARNING:x4kma:340 - Signal "GLOBAL LOGICO" on pin BO of CY4 symbol

mode

been



mode-reduced. The original carry mode was "ADDSUB-F-CI".

WARNING:x4kma:340 - Signal I r& A 40" on pin ADD of CY4 symbol "H4/$Ill/ $1197"

"

(output signal=H4/$111/C2) is not required by carry mode EXAMINE-CI. The



WARNING:x4kma:340 - Signal 'I& A 68" on pin A0 of CY4 symbol "H5/$Ill/ $1197"

(output signal=HS/$Ill/C2) is not required by carry mode EXAMINE-CI. The

signal i s being removed. This carry component has been mode-reduced. The

"

original carry mode waS "ADDSUB-F-CI".


mode

been




WARNING:x4kma:340 - Signal " & A 65" on pin ADD of CY4 symbol "H5/$Ill/ $1197"

"

(output signal=H5/$11l/C2) is not required by carry mode EXAMINE-CI. The

original carry mode was "ADDSUB-F-CI".

WARNING:x4kma:340 - Signal I r & A 93" on pin A0 of CY4 symbol "HG/$Ill/ $1197"

,(output siqnal=HG/$Ill/C2) is not required by carry mode EXAMINE-CI. The

signal is being removed. This carry component has been mode-reduced. The



mode

been

"H6/$111/$1197" (output signal=HG/$Ill/C2) is not required by carry



(output signal=HG/$Ill/C2) is not required by carry mode EXAMINE-CI.



The

The

(output signal=H8/$111/C2) is not required by carry mode EXAMINE-CI. The


original carry mode was "ADDSUB-F-CIff. The

WARNING:x4kma:340 - Signal " & A 115" on pin ADD of CY4 symbol "He/ $Ill/$1197"

The

"

(Output signal=H8/$111/C2) is not required by carry mode EXAMINE-CI.

Signal is being removed. This carry component has been mode-reduced. The

original carry mode was "ADDSUB-F-CI" .

Section 3 - Design Attributes """"""""""""""- 2 2 5 8 & 6 Section 4 - Removed Logic Summary """"""""""""""""- 369 block ( S ) removed

358 signal ( S ) removed 34 block(s) optimized away

Section 5 - Removed Logic """"""""""""-

The trimmed logic report below shows the logic removed from your design due to sourceless or loadless signals, and VCC or ground connections. I f the removal of a signal or symbol results in the subsequent removal of an additional signal or symbol, the message explaining that second removal will be indented. This indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look above the place where that logic is listed in the trimming report, then locate the lines that are least indented (begin at the leftmost edge).

Loadless block "H10/$110" (XNOR2) removed. Loadless block "H3/$111/$1183" (CY4) removed. Loadless block "H4/$111/$1183" (CY4) removed. Loadless block "H5/$111/$1183" (CY41 removed. Loadless block "H6/$111/$1183" (CY4) removed. Loadless block "H8/$111/$1183" (CY4) removed.

The trimmed logic reported below is either: 1. part of a cycle 2. part of disabled logic 3. a side-effect of other trimmed logic

The signal "H10/$16/B3 M2" is unused and has been removed.

The signal "HlO/$I6/CO" is unused and has been removed. Unused block "H10/$16/$11278" (XNOR2) removed.

Unused block "HlO/$I6/$lI237/HlO/$I6/CO" (X-OR2) removed. The signal "H10/$16/C0/2.0" is unused and has been removed.

The signal "H10/$16/CORlf' is unused and has been removed.

The signal "H10/$16/COR2" is unused and has been removed.

Unused block "HlO/$I6/$11237/HlO/$16/CO/2.0" (X-OR2) removed.

Unused block "H10/$16/$11234" (AND2) removed.

Unused block "H10/$16/$11235" (AND2) removed. The signal "H10/$16/COR3" is unused and has been removed. Unused block "H10/$16/$11236" (AND2) removed.

The signal "Hl/$Il/B3 M2" is unused and has been removed.

The signal "Hl/$Il/CO" is unused and has been removed. Unused block "H1/$11/$11278" (XNOR2) removed.

Unused block "H1/$11/$11237/H1/$Il/CO" (X OR2) removed. The signal "H1/$11/C0/2.0f' is unused and-has been removed. Unused block "H1/$11/$11237/H1/$11/C0/2.0" (X-OR2) removed.

The signal "H1/$Il/COR1" is unused and has been removed.

The signal "Hl/$IL/COR2" is unused and has been removed. Unused block "H1/$11/$11234" (AND2) removed.

Unused block "H1/$11/$11235" (AND2) removed. The signal "Hl/$Il/COR3" is unused and has been removed. Unused block "H1/$11/$11236" (AND2) removed.

The signal "H1/$113/$Net00273 " is unused and has been removed. Unused block "H1/$113/$11260/H1/$113/$Net00273 'I (X-OR2) removed. The signal "Hl/$I13/$Net00273 /2.0" is unused-and has been removed. Unused block "H1/$113/$11260/Hl/$I13/$Net00273 /2.0" (X OR2) removed. The signal "Hl/$I13/00Rl" is unused and has been removed. Unused block "H1/$113/$11266" (ANDZ) removed. The signal "H1/$113/B3 M1" is unused and has been removed. Unused block "Hl/$T137$11271' (XNOR2) removed

The signal "Hl/$I13/00R2" is unused and has been removed. Unused block "H1/$113/$11270" (AND2) removed.


The signal "Hl/$I13/0FL" is unused and has been removed.

The signal "Hl/$I16/$Net00273 'I is unused and has been removed. Unused block "H1/$113/$11305" (XOR2) removed.

Unused block "H1/$116/$11260/H1/$116/$Net00273_" (X-OR2) removed. The signal "Hl/$I16/$Net00273 /2.0" is unused and has been removed. Unused block "H1/$116/$11260/H1/$116/$Net00273~/2.0'' (X-OR2) removed. The signal "H1/$116/00R1" is unused and has been removed. Unused block "H1/$116/$11266" (AND2) removed. The signal "H1/$116/B3 M1" is unused and has been removed. Unused block "H1/$116~$11271" (XNOR2) removed.

The signal "H1/$116/00R2" is unused and has been removed. Unused block "H1/$116/$11270" (AND2) removed.


The signal "Hl/$I16/OFL" is unused and has been removed.

The signal "Hl/$I18/$Net00273 is unused and has been removed. Unused block "H1/$116/$11305' (XOR2) removed.

Unused block "H1/$118/$11260/H1/$118/$Net00273 'I (X OR2) removed. The signal "Hl/$I18/$Net00273 /2.0" is unused-and has been removed. Unused block "H1/$I18/$11260/H1/$118/$NetOOZ73 /2.0" (X OR2) removed. The signal "Hl/$I18/00Rl" is unused and has been removed. Unused block "H1/$118/$11266" (AND2) removed. The signal "H1/$118/B3 M1" is unused and has been removed. Unused block "H1/$118~$11271" (XNOR2) removed.

The signal "Hl/$I18/00R2" is unused and has been removed. Unused block "H1/$I18/$1127O1' (AND2) removed.


The signal "H1/$118/0FL1' is unused and has been removed.


The signal "H1/$14/CO" is unused and has been removed.

Unused block "H1/$118/$11305" (XOR2) removed.

Unused block "H1/$14/$11278" (XNOR2) removed.

Unused block "Hl/$I4/$11237/H1/$14/CO" (X-OR2) removed. The signal "Hl/$I4/C0/2.0" is unused and has been removed. Unused block "Hl/$I4/$11237/H1/$14/CO/2.0" (X-OR2) removed. The signal "Hl/$I4/CORl" is unused and has been removed.

The signal "Hl/$I4/COR2" is unused and has been removed. Unused block "H1/$14/$11234" (AND2) removed.

Unused block "H1/$14/$11235" (AND2) removed. The signal "Hl/$I4/COR3" is unused and has been removed. Unused block "H1/$14/$11236" (AND21 removed.

The signal "Hl/$I8/B3-M2" is unused and has been removed.


Unused block "H1/$18/$11237/Hl/$18/CO" (X-OR2) removed. The signal "H1/$18/CO" is unused and has been removed.

The signal "H1/$18/C0/2.01' is unused and has been removed. Unused block "H1/$18/$11237/Hl/$I8/CO/2.0" (X OR2) removed. The signal "Hl/$I8/CORl" is unused and has been removed.

The signal "Hl/$I8/COR2" is unused and has been removed. Unused block "H1/$18/$11234" (AND2) removed.

Unused block "H1/$18/$11235" (AND2) removed. The signal "Hl/$I8/COR3" is unused and has been removed. Unused block "H1/$18/$11236" (AND2) removed.

The signal "H3/$Ill/$Net00273-" is unused and has been removed. Unused block "H3/$111/$11260/H3/$Ill/$NetO0273~w (X OR2) removed. The siqnal "H3/$Ill/$Net00273 /2.0" is unused and zas been removed. Unused block "H3/$111/$11260/H3/$111/$Net00273~/2.0~~ (X-OR2) removed. The signal "H3/$111/00Rl" is unused and has been removed. Unused block "H3/$111/$11266" (AND2) removed. The signal "H3/$Ill/B3 M1" is unused and has been removed. Unused block "H3/$111/$11271" (XNOR2) removed.


The signal "H3/$111/00R3" is unused and has been remo.ved. Unused block "H3/$111/$11264" (AND2) removed.

The signal "H3/$Ill/B3 M2" is unused and has been removed.

The signal "H3/$111/C01' is unused and has been removed. Unused block "H3/$111/$11278" (XNOR2) removed.

Unused block '1H3/$111/$11237/H3/$Ill/CO" (X-OR2) removed. The signal "H3/$Ill/C0/2.0" is unused and has been removed.


The signal "H3/$Ill/COR2" is unused and has been removed.

Unused block "H3/$111/$11237/H3/$Ill/CO/2.0" (X OR2) removed.


Unused block "H3/$111/$11235" (AND2) removed. The signal "H3/$Ill/COR3" is unused and has been removed. Unused block ''H3/$111/$11236" (AND2) removed.

The signal "H3/$113/$NetO0273_" is unused and has been removed. Unused block "H3/$113/$11260/H3/$113/$Net00273_" (X OR2) removed. The signal "H3/$113/$Net00273 /2.0" is unused and has been removed. Unused block "H3/$113/$11260/H3/$113/$NetO0273~/2.0~v (X-OR2) removed. The signal "H3/$113/00Rl" is unused and has been removed. Unused block "H3/$113/$11266" (AND2) removed. The signal "H3/$113/B3 M1" is unused and has been removed. Unused block "H3/$113/$11271" (XNOR2) removed.



The signal "H3/$113/0FL" is unused and has been removed.

The signal "H3/$116/$Net00273-" is unused and has been removed. Unused block "H3/$113/$11305" (XORZ) removed.

Unused block "H3/$116/$11260/H3/$116/$Net00273_" (X OR2) removed. The signal "H3/$116/$NetO0273 /2.0" is unused and 6as been removed. Unused block "H3/$116/$11260/H3/$116/$Net00273_/2.0" (X-OR2) removed. The signal "H3/$116/00Rl" is unused and has been removed. Unused block "H3/$116/$11266" (AND2) removed. The signal "H3/$116/B3 M1" is unused and has been removed. Unused block "H3/$116/$11271" (XNOR2) removed.

The signal "H3/$116/00R2" is unused and has been removed. Unused block "H3/$116/$11270" (AND21 removed.


The signal "H3/$116/0FL" is unused and has been removed.

The signal "H3/$118/$Net00273-" is unused and has been removed. Unused block "H3/$116/$11305" (XOR2) removed.

Unused block "H3/$118/$11260/H3/$118/$Net00273 'I (X-OR2) removed. The signal "H3/$118/$NetO0273 /2.0" is unused-and has been removed. Unused block "H3/$I18/$1I260/H3/$I18/$NetOO273 /2.0" (X-OR2) removed. The signal "H3/$115/00R1" is unused and has been removed. Unused block "H3/$118/$11266" (AND2) removed. The signal "H3/$118/B3 M1" is unused and has been removed. Unused block "H3/$1187$11271" (XNOR2) removed.


The signal "H3/$118/OOR3" is unused and has been removed. Unused block "H3/$118/$11264' (AND2) removed.

The signal "H3/$118/OFL" is unused and has been removed.

The signal "H3/$13/B3 M2"'is unused and has been removed.




Unused block "H3/$13/$11237/H3/$13/CO" (X OR2) removed. The signal "H3/$13/C0/2.01' is unused and-has been removed. Unused block "H3/$13/$11237/H3/$13/C0/2.0" (X-OR2) removed. The signal "H3/$13/CORl" is unused and has been removed.

The signal "H3/$13/CGR2" is unused and has. been removed. Unused block "H3/$13/$11234" (AND2) removed.



The signal "H3/$16/CO" is unused and has been removed. Unused block "H3/$16/$11278" (XNGR2) removed.

Unused block "H3/$16/$11237/H3/$16/CO" (X-OR2) removed. The signal "H3/$16/C0/2.01' is unused and has been removed. Unused block "H3/$I6/$11237/H3/$16/C0/2.0" (X OR2) removed. The signal "H3/$16/COR11' is unused and has been removed.

The signal "H3/$16/COR2" is unused and has been removed. Unused block "H3/$16/$11234" (AND2) removed.

Unused block "H3/$16/$11235" (AND2) removed. The signal "H3/$16/COR3" is unused and has been removed.

The signal "H3/$Net00054-" is unused and has been removed. Unused block "H3/$111/$11305" (XOR2) removed. The signal "H3/$Net00055 'I is unused and has been removed. Unused block "H3/$Ill/S~/H3/$NetOOO55_" (X XOR2) removed.

Unused block "H3/$16/$11236" (ANDZ) removed.

The signal "H3/$Net00055 /2.0" is unused and has been removed. Unused block "H3/$Ill/S3/H3/$NetOOO55 /2.0" (X-XOR2) removed.

The signal "H3/$Net00055 /2.1" is unused and has been removed. Unused block "H3/$Ill/S~/H3/$NetOOO55 /2.1" (X-XOR2) removed.

Unused block "H4/$Ill/$1126O~H4/$Ill/$Net00273~~' (X OR21 removed. The signal "H4/$Ill/$Net00273 'I is unused and has been removed.

The signal "H4/$Ill/$Net00273 /2.0" is unused and has been removed. Unused block "H4/$111/$11260~H4/$111/$Net00273~/2.0~~ (X-OR2) removed. The signal "H4/$111/00R1" is unused and has been removed. Unused block "H4/$111/$11266" (AND2) removed. The signal "H4/$Ill/B3 M1" is unused and has been removed. Unused block "H4/$111/$11271" (XNOR2) removed.



The signal "H4/$Ill/B3 - M2" is unused and has been removed.




The signal "H4/$16/CO" is unused and has been removed. Unused block "H4/$16/$11278" (XNOR2) removed.

Unused block "H4/$16/$11237/H4/$16/CO" (X OR2) removed. The signal "H4/$16/C0/2.0" is unused and-has been removed. Unused block "H4/$16/$11237/H4/$16/C0/2.0" (X OR2) removed. The signal "H4/$16/CORl" is unused and has been removed.


1Jnl.lsed bLock "H4/$16/$11235" ( A N D 2 ) removed. The signal "H4/$16/COR3" is unused and has been removed.

The signal "H4/$Net00054 " is unused and has been removed. Unused block "H4/$111/$¡1305" (XOR2) removed.

The signal "H4/$Net00055 " is unused and has been removed. Unused block "H4/$Ili/S~/H4/$NetOOO55~~~ (X XOR2) removed.


The signal "H4/$Net00055 /2.0" is unused and has been removed. Unused block "H4/$Ill/S~/H4/$NetO0055-/2.0" (X-XOR2) removed.

The signal "H4/$NetOOO55 /2.1" is unused and has been removed. Unused block '1H4/$Ill/S~/H4/$NetOO055 /2.1" (X-XOR2) removed.

Unused block "H5/$111/$11260~H5/$111/$Net00273_" (X OR2) removed. The signal "H5/$Ill/$Net00273 'I is unused and has been removed.

The signal "H5/$Ill/$Net00273 /2.0" is unused and has been removed. Unused block "H5/$111/$11260/H5/$Ill/$Net00273 /2.0" (X-OR2) removed. The signal "H5/$111/0OR1" is unused and has been removed. Unused block "H5/$111/$11266" (AND2) removed. The signal "H5/$Ill/B3 M1" is unused and has been removed. Unused block "H5/$111~$11271" (XNOR2) removed.


The signal "H5/$111/0OR3" is unused and has been removed. Unused block "H5/$111/$11264" (AND2) removed.

The signal "'?5/$Ill/B3 M2" is unused and has been removed.

The signal "H5/$111/CO" is unused and has been removed. Unused blc,-rc "H5/$1117$11278" (XNOR2) removed.

Unused block "H5/$111/$11237/H5/$Ill/CO" (X-OR2) removed. The signal "H5/$Ill/C0/2.0" is unused and has been removed.

The signal "H5/$111/CORl" is unused and has been removed.


Unused block "H5/$Ill/$11237/H5/$Ill/CO/2.0f' (X-OR2) removed.


Unused block "H5/$111/$11235" (AND2) removed. The signal "H5/$Ill/COR3" is unused and has been removed. Unused block "H5/$111/$11236" (AND2) removed.

The signal "H5/$113/$Net08273-" is unused and has been removed. Unused block "H5/$113/$11260/H5/$113/$Net00273_" (X OR2) removed. The signal "H5/$113/$NetO0273 /2.0" is unused and has been removed. Unused block "H5/$113/$11260~H5/$113/$Net00273_/2.0" (X-OR2) removed. The signal "H5/$113/00R1" is unused and has been removed. Unused block "H5/$113/$11266" (AND2) removed. The signal "H5/$113/B3 M1" is unused and has been removed. Unused block "H5/$113/$11271" (XNOR2) removed.



The sianal "H5/SI13/OFL" is unused and has been removed.


Unused block "H4/$111/$11237/H4/$Ill/CO" (X OR2) removed. The signal "H4/$111/CO" is unused and has been removed.

The signal "H4/$Ill/C0/2.0'' is unused and has been removed.

The signal "H4/$111/CORl" is unused and has been removed,


Unused block "H4/$I11/$1I237/H4/$Ill/C0/2.0" (X OR2) removed.



The signal "H4/$113/$Net00273 I' is unused and has been removed. Unused block "H4/$113/$11260/H4/$113/$Net00273 'I (X OR2) removed. The signal. "H4/$11,3/SNet00273 /2.0" i.s Ilnused-and Las been removed. Unused block "H4/$113/$11260/H4/$113/$Net00273 /2.0" (X OR2) removed. The signal "H4/$113/00Rl" is unused and has been removed. Unused block "H4/$113/$11266" (AND2) removed. The signal "H4/$113/B3 M1" is unused and has been removed. Unused block "H4/$1137$11271" (XNOR2) removed.




The signal "H4/$116/$Net00273 I' is unused and has been removed. Unused block "H4/$113/$11305" (XOR2) removed.

Unused block "H4/$I16/$11260~H4/$I16/$Net00273 I' (X-OR2) removed. The signal "H4/$116/$NetO0273 /2.0" is unused-and has been removed. Unused block "H4/$116/$11260~H4/$116/$Net00273 /2.0" (X OR2) removed. The signal "H4/$116/00R1" is unused and has been removed. Unused block "H4/$116/$11266" (AND2) removed. The signal "H4/$116/B3 M1" is unused and has been removed. Unused block "H4/$116~$11271' (XNOR2) removed.




The signal "H4/$118/$Net00273 I' is unused and has been removed. Unused block "H4/$116/$11305" (XOR2) removed.

Unused block "H4/$118/$11260/H4/$118/$Net00273_" (X OR2) removed. The signal "H4/$118/$NetO0273 /2.0" is unused and has been removed. Unused block "H4/$I18/$1I260/H4/$I18/$Net00213 /2.0" (X-OR2) removed. The signal "H4/$118/00Rl" is unused and has been removed. Unused block "H4/$118/$11266" (AND2) removed. The signal "H4/$118/B3 M1" is unused and has been removed. Unused block "H4/$1187$11271" (XNOR2) removed.


The signal "H4/$118/00R3" is unused and has been removed. Unused block "H4/$118/$11264' (AND2) removed.






Unused block "H4/$13/$11237/H4/$13/CO" (X OR2) removed. The signal "H4/$13/CO/2.0" is unused and-has been removed. Unused block "H4/$13/$11237/H4/$13/CO/2.0" (X-OR2) removed. The signal "H4/$13/CORl" is unused and has been removed. Unused block "H4/$13/$11234" (AND2) removed.


Unused block "H5/$116/$11260~H5/$116/$Net00273 " (X-OR2) removed. The signal "H5/$116/$NetO0273 " is unused and has been removed.

The signal "H5/$116/$NetO0273 /2.0" is unused-and has been removed. Unused block "H5/$116/$11260iH5/$116/$Net00273 /2.0" (X-OR2) removed. The signal "H5/$116/00Rl" is unused and has been removed. Unused block "H5/$116/$11266" (AND2) removed. The signal "H5/$116/83 MI" is unused and has been removed. Unused block "H5/$1167$11271" (XNOR2) removed.

The signal "H5/$116/OOR2" is unused and has been removed. Unused block "H5/$116/$11270" (AND2) removed.


The sigml "H5/$116./0FL" i s unmad 2F.d has been remc-:ed.

The signal "H5/$118/SNet00273 " is unused and has been removed. Unused block "H5/$116/$11305" (XOR2) removed.

Unused block "H5/$118/$11260~H5/$118/$Net00273_" (X-OR2) removed. The signal "H5/$118/$NetO0273 /2.0" is unused and has been removed. Unused block "H5/$118/$11260/H5/$118/$Net00273 /2.0" (X OR2) removed. The signal "H5/$118/00Rl" is unused and has been removed. Unused block "H5/$118/$11266" (AND2) removed. The signal "H5/$118/B3 M1" is unused and has been removed. Unused block "H5/$1187$11271" (XNOR2) removed.


The signal "H5/$118/0OR3" is unused and has been removed. Unused block "H5/$118/$11264" (AND21 removed.





Unused block "H5/$137$11278" (XNOR2) removed.

Unused block "H5/$13/$11237/H5/$13/CO" (X-OR2) removed. The signal "H5/$13/CO/2.0" is unused and has been removed. Unused block "H5/$13/$11237/H5/$13/C0/2.0" (X OR2) removed. The signal "H5/$13/CORlf' is unused and has been removed.





Unused block "H5/$16/$11237/H5/$16/CO" (X-OR2) removed. The signal "H5/$16/C0/2.O1' is unused and has been removed. Unused block "H5/$16/$11237/H5/$16/C0/2.0" (X OR2) removed. The signal "H5/$16/CORl" is unused and has been removed.


Unused block "H5/$16/$11235" (AND21 removed. The signal "H5/$16/COR3" is unused and has been removed.

The signal "H5/$NetOO054 " is unused and has been removed. Unused block "H5/$Ill/$iI305" (XOR2) removed.

The signal "H5/$Net00055-" is unused and has been removed. Unused block "H5/$Ill/S3/H5/$NetO0055-" (X X O R 2 ) removed.


The signal "H5/$NetO0055 /2.0" is unused and has been removed. Unused block "H5/$Ill/S3/H5/$NetOOO55 /2.0" (X-XOR2) removed. The signal "H5/$Net00055 /2.1" is unused and has been removed. Unused block " H 5 / $ I l l / S ~ / H 5 / $ N e t O O 0 5 5 _ / 2 . 1 " (X-XOR2) removed.

The signal "H6/$Ill/$Net00273 " is unused and has been removed. Unused block "H6/$111/$11260/H6/$Ill/$Net00273 " (X OR2) removed. The signal "H6/$Ill/$Net00273 /2.0" is unused-and has been removed. Unused block "H6/$111/$11260/H6/$Ill/$Net00273 /2.0" (X OR2) removed The signal "H6/$111/00RI" is unused and has been removed. Unused block "H6/$11~/$11266" (AND2) removed. The signal "H6/$Ill/B3 M1" is unused and has been removed. Unused block "H6/$illT$li271" (XNOR2) removed.

The signal "H6/$111/00R2" is unused and has been removed. Unused block "H6/$111/$1127@" (AND2) removed.



The signal "H6/$111/C01' is unused and has been removed. Unused block "H6/$111~$11278" (XNOR2) removed.

Unused block "H6/$111/$11237/H6/$111/C0" (X OR2) removed. The signal "H6/$Ill/C0/2.0" is unused and gas been removed.



Unused block "H6/$Ill/$l1237/H6/$Ill/CO/2.0" (X OR2) removed.


Unused block "H6/$111/$11235" (AND2) removed. The signal "H6/$Ill/COR3" is unused and has been removed. Unused block "H6/$ill/$lI236" (AND2) removed.

The signal "H6/$113/$NetO0273 " is unused and has been removed. Unused block "H6/$113/$11260/H6/$113/$NetO0273 I' (X OR2) removed. The signal "H6/$113/$Net@0273 /2.0" is unused-and has been removed. Unused block "H6/$113/$11260/H6/$113/$Net00273 /2.0" (X OR2) removed The signal "H6/$113/00Rl" is unused and has been removed. Unused block "H6/.$113/$11266" (AND2) removed. The signal "H6/$1131B3 M1" is unused and has been removed. Unused block "H6/$113~$11271" (XNOR2) removed.

The signal "H6/$113/00R2" is unused and has been removed. Unused block "H6/$113/$11270" (ANDí!) removed.

The signal "H6/$113/0OR3" is unused and has been removed. Unused block "H6/$113/$11264" (AND21 removed.


The signal "H6/$116/$NetO0273 I' is unused and has been removed. Unused block "H6/$113/$11305" (XOR2) removed.

Unused block "H6/$116/$11260/H6/$116/$Net00273 " (X-OR2) removed. The signal "H6/$116/$NetO0273 /2.0" is unused-and has been removed. Unused block "H6/$116/$11260/H6/$116/$Net00273~/2.0" (X-OR2) removed. The signal "H6/$116/00Rl" is unused and has been removed. Unused block "H6/$116/$11266" (AND2) removed. The signal "H6/$116/B3 M1" is unused and has been removed. Unused block "H6/$116/S11271" (XNOR2) removed.





Unused block "H6/$118/$11260/H6/$118/$Net00273_" (X OR2) removed. The signal "H6/$118/$NetO0273 /2.0" is unused and Eas been removed. Unused block "H6/$118/$11260~H6/$118/$Net00273~/2.0" (X-OR2) removed The signal "H6/$118/0ORl" is unused and has been removed. Unused block "H6/$118/$11266" (AND2) removed. The signal "H6/$118/B3 M1" is unused and has been removed. Unused block "H6/$118/$11271" (XNOR2) removed.

The signal "H6/$118/00R2" is unused and has been removed.

Unused block "H6/$118/$11270" (AND2) removed. The signal "H6/$118/OOR3" is unused and has been removed. Unused block "H6/$118/$11264" (AND2) removed.




Unused block "H6/$118/$11305" (XCR2) removed.


Unused block "H6/$13/$11237/H6/$13/C01' (X OR2) removed. The signal "H6/$13/C0/2.01' is unused and-has been removed. Unused block "H6/$13/$11237/H6/$13/C0/2.0" (X OR2) removed. The signal "H6/$I3/CORl1' is unused and has been removed.

The signal ":iG/$I3/CCR2" is L;nussd aad has been removed. Unused block "H6/$13/$11234" (AND21 removed.



The signal "H6/$16/C01' is unused and has been removed. Unused block "H6/$16/$11278" (XNOR2) removed.

Unused block "H6/$16/$11237/H6/$16/CO" (X OR2) removed. The signal "H6/$16/C0/2.0" is unused and-has been removed. Unused block "H6/$16/$i1237/H6/$16/CO/2.0" (X-OR2) removed. The signal "H6/$16/CORl" is unused and has been removed.



The signal "H6/$Net00054 " is unused and has been removed. Unused block "H6/$111/$¡1305' (XOR2) removed. The signal "H6/$Net00055 " is unused and has been removed. Unused block "H6/$Ill/S~/H6/$NetOO055-1' (X XOR2) removed.


The signal "H6/$Net00055 /2.0" is unused and has been removed. Unused block "H6/$Ill/S~/H6/$NetO0055-/2.0" (X-XOR2) removed.

The signal "H6/$Net00055 /2.1" is unused and has been removed. Unused block "H6/$Ill/S~/H6/$NetOOO55 /2.1" (X XOR2) removed.

Unused block "H8/$Ill/$11260/H8/$Ill/$Net00273 'I (X-OR2) removed. The signal "H8/$Ill/$Net00273-" is unuse3 and has-been removed.

The signal "H8/$Ill/$Net00273 /2.0" is unused-and has been removed. Unused block "H8/$111/$11260~H8/$Ill/$Net00273 /2.0" (X-OR2) removed The signal "H8/$111/00Rl" is unused and has been removed. Unused block "H8/$111/$11266" (AND2) removed. The signal "H8/$Ill/B3 M1" is unused and has been removed. Unused block "H8/$1117$11271" (XNOR2) removed.





Unused block "H8/$111/$11237/H8/$11l/CO" (X OR2) removed. The signal "H8/$Ill/C0/2.0" is unused and has been removed.



Unused block "H8/$111/$11237/H8/$1ll/CO/2.0" (X-OR2) removed.


Unused block "H8/$111/$11235" (AND2) removed. The signal "H8/$Ill/COR3" is unused and has been removed. Unused block "H8/$111/$11236" (AND2) removed.

The signal "H8/$113/$Net00273-" is unused and has been removed. Unused block "H8/$113/$11260/H8/$113/$Net00273 'I (X-OR2) removed. The signal "H8/$113/$NetO0273 /2.0" is unused-and has been removed. Unused block "H8/$113/$11260/H8/$113/$Net00273~/2.0'~ (X-OR2) removed. The signal "H8/$113/00Rl" is unused and has been removed. Unused block "H8/$113/$11266" (AND2) removed. The signal "H8/$113/B3 M1" is unused and has been removed. Unused block "H8/$1137$11271" (XNOR2) removed.

The signal "H8/$113/GOR2" is unused and has been removed. Unused block "H8/$113/$11270" (AND2) removed.



The signal "H8/$116/$NetO0273 I' is unused and has been removed. 'Jnused block "HS/$;i3/$li305" (XOR.2) removed.

Unused block "H8/$116/$11260~H8/$116/$Net00273 '' (X OR2) removed. The signal "H8/$116/$Net00273 /2.0" is unused-and has been removed. Unused block "H8/$116/$11260/H8/$116/$Net00273 /2.0" (X-OR2) removed. The signal "H8/$116/OORl" is unused and has been removed. Unused block "H8/$116/$11266" (AND2) removed. The signal "H8/$116/B3 M1" is unused and has been removed. Unused block "H8/$1167$11271" (XNOR2) removed.



The signal "H8/$I16/0FL1' is unused and has been removed.


Unused block "H8/$118/$11260/H8/$118/$Net00273~" (X OR2) removed. The signal "H8/$118/$NetO0273 /2.0" is unused and has been removed. Unused block "H8/$118/$11260~H8/$118/$Net00273~/2.0~~ (X-OR2) removed. The signal "H8/$118/00R1" is unused and has been removed. Unused block "H8/$118/$11266" (AND2) removed. The signal "H8/$118/B3-M11' is unused and has been removed. Unused block "H8/$118/$11271" (XNOR2) removed.





The signal "H8/$13/COf' is unused and has been removed.


Unused block "H8/$137$11278" (XNOR2) removed.

Unused block "H8/$13/$11237/H8/$13/CO" (X OR2) removed. The signal "H8/$13/C0/2.0" is unused and-has been removed. Unused block "H8/$13/$11237/H8/$13/C0/2.0" (X OR2) removed. The signal "H8/$13/CGR11' is unused and has been removed.

The signal "H8/$13/COR2" is unused and has been removed. Unused block "H8/$13/$11234'' (AND2) removed.



The signal "H8/$16/CG" is unused and has been removed. Unused block "H8/$16/$11278" (XNOR2) removed.

Unused block "H8/$16/$11237/H8/$16/CO" (X-OR2) removed. The signal "H8/$16/C0/2.0" is unused and has been removed. Unused block "H8/$16/$11237/H8/$16/C0/2.0" (X OR2) removed. The signal "H8/$16/CORl" is unused and has been removed.



The signal "H8/$16/COR3* is unused and has been removed.

The signal "H8/$Net00054-" is unused and has been removed. Unused block "H8/$111/$1I305" (XOR2) removed.

The signal "H8/$Net00055 'I is unused and has been removed. Unused block "H8/$Ill/S~/H8/$NetOOO55 " (X-XOR2) removed.


The signal "H8/$Net00055 /2.0" is unused and has been removed. Unused block "H8/$Ill/S~/H8/$NetOOO55 /2.0" (X XOR2) removed. The signal "H8/$Net00055 /2.1" is unused and has been removed. Unused block "H8/$Ill/S?/H8/$NetOOO55 /2.1" (X XOR2) removed.

The signal "HlO/$Ill/B3 M2" is unused and has been removed.

The signal "HlO/$Ill/CO" is unused and has been removed. Unused block "HlO/$Ill/$11278" (XNOR2) removed.

Unused block "HlO/$Ill/$1I237/HlO/$Ill/CO" (X OR2) removed. The signal "H10/$111/C0/2.0" is unused and has been removed.


The signal "HlO/$Ill/COR2" is unused and has been removed.

Unused block "HlO/$I11/$1I237/HlO/$Ill/C0/2.0" (X OR2) removed.


Unused block "H10/$111/$11235" (AND2) removed. The signal "HlO/$Ill/COR3" is unused and has been removed. Unused block "H10/$111/$11236" (AND2) removed.

The signal "Hl0/$113/$Net00273 " is unused and has been removed. Unused block "H10/$113/$11260/H10/$113/$Net00273_" (X-OR2) removed.

Unused block "H10/$113~$11260¡H10/$113/$Net00273 /2.0" (X-OR2) The signal "H10/$113/$Net00273 /2.0" is unused and has been removed.

removed. -

The signal "H10/$113/00Rl" is unused and has been removed. Unused block "H10/$113/$11266" (AND2) removed. The signal "H10/$113/B3 M1" is unused and has been removed. Unused block "H10/$I13/$11271" (XNOR2) removed.


The signal "H10/$113/00R3" is unused and has been removed. Unused block "H10/$113/$11264," (AND2) removed.

The signal "H10/$€13/OFL" is unused and has been removed.

The signal "Hl0/$116/$Net00273 " is unused and has been removed. Unused block "H10/$113/$11305" (XOR2) removed.

Unused block "H10/$116/$11260/H10/$116/$Net00273 " (X-OR2) removed.

Unused block "H10/$116/$11260/H10/$116/$Net00273 /2.0" (X-OR2) The signal "Hl0/$116/$Net00273 /2.0" is unused and has been removed.

removed. -

The signal "H10/$116/00Rl" is unused and has been removed. Unused block "H10/$116/$11266" (AND2) removed. The signal "H10/$116/B3 M1" is unused and has been removed. Unused block "H10/$116¡$1I271" (XNOR2) removed.


The signal "Hl0/$116/00R3" is unused and has been removed. Unused block "H10/$116/$11264" (AND2) removed.

The signal "HlO/$I16/OFL" is unused and has been removed.

The signal "HlO/$I18/$Net00273-" is unused and has been removed. Unused block "H10/$116/$II305" (XOR2) removed.

Unused block "H10/$118/$11260/H10/$118/$Net00273~" (X OR2) removed.

Unused block "H10/$118/$11260/H10/$118/$Net00273~/2.0" (X-OR2) The signal "Hl0/$118/$Net00273 /2.0" is unused and has been removed.

removed. The signal "H10/$118/00Rl" is unused and has been removed.

Unused block "H10/$118/$11266" (AND2) removed. The signal "H10/$118/B3 M1" is unused and has been removed. Unused block "H10/$118/$11271" (XNOR2) removed.


The signal "H10/$118/0OR3" is unused and has been removed. Unused block "H10/$118/$11264" . (AND2) removed.

The signal "HlO/$I18/OFL" is unused and has been removed.


The signal "HlO/$I3/CO" is unused and has been removed.



Unused block "HlO/$I3/$1I237/HlO/$I3/CO" (X OR2) removed. The sicpal "€!lO/SI3/CC/2.Or' is unused 2nd has beer, remsvcd.

The signal "HlO/$I3/CORl" is unused and has been removed.


-

Unused block "H10/$13/$11237/H10/$13/C0/2.0" (X OR2) removed.



The signal " & " A 32" is unused and has been removed. Unused block "H8/$17" (XOR2) removed.

The signal 'I& " A 36" i s unused and has been removed. Unused block "H8/$113/S3/& A 36" (X XOR2) removed. The signal Ir& A 36/2.0" is unused and has been removed. Unused block "H8/$113/S3/& " A 36/2.0" (X-XOR2) removed.

"

"

The signal "H8/$113/S3/& A 11/3" is unused and has been removed. Unused block "H8/$113/S3/H8/& A 11" (X-XOR2) removed.

The signal " & A 37" is unused and has been removed. Unused block "H8/$113/S2/& A 37" (X XOR2) removed.

"

"

"

The signal Ir& A 37/2.0" is unused and has been removed. Unused block7H8/$113/S2/& " A 37/2.0" (X XOR2) removed.

The signal 'I& A 37/2.1" is unused and has been removed. Unused block "H8/$113/S2/& " A 37/2.1" (X XORZ) removed.

The signal " & A 38" i s unused and has been-removed. Unused block"H8/$113/Sl/& " A 38" (X XOR2) removed. The signal " & A-38/2. O" i s unused and has been removed. Unused block~H8/$113/Sl/& A 38/2.0" (X-XOR2) removed. The signal "H8/$113/Sl/& A 11/3" i s unused and has been removed.

"

"

Unused block "H8/$113/Sl/H8/& " A 11" (X XOR2) removed. The signal I r& A 39" is unused and has been removed. Unused block"H8/$113/SO/& A &39'' (X XOR2) removed. The signal " & A 39/2.0" is unused and has been removed. Unused block7H8/$113/SO/& A 39/2.0" (X XOR2) removed. The signal " & A-39/2.1" is unused and has been removed. Unused block7H8/$113/SO/& " A 39/2.1" (X-XORZ) removed.

"

The signal "&-A 41" is unused and has been removed. Unused block "H3/$17" (XOR2) removed. The signal " & A 66" is unused and has been removed. Unused block7H4/$17" (XOR2) removed.

The signal Ir& A 73" is unused and has been removed. Unused block"H4/$113/SO/& A 73" (X-XOR2) removed. The signal I r& A 13/2.0" is unused and has been removed. Unused block "H4/$113/SO/& A 73/2.0" (X XORZ) removed.

Unused block "H4/$113/SO/H4/& A 5" (X XOR2) removed.

"

The signal "H4/$113/SO/& A 5/2" is unused and has been removed. "

The signal " & A 91" is unused and has been-removed. Unused block "H5/$17" (XOR2) removed. The signal " & A 97" is unused and has been removed. Unused block "H5/$113/Sl/& " A 97" (X - XOR2) removed.

The signal " & " A 97/2.0" is unused and has been removed. Unused block "H5/$113/Sl/&-A 97/2.0" (X-XOR2) removed.

Unused block "H5/$113/Sl/H5/&-A 7" (X XOR2) removed. The signal "H5/$113/Sl/& A 7 / 3 " is unused and has been removed.

The signal l r& -- A 98" is unused and has been-removed. Unused block "H5/$113/SO/& A 98" (X XOR2) removed. The signal " & A 98/2.0" is unused and has been removed. Unused block "H5/$113/SO/& -- A 98/2.0" (X XOR2) removed.

Unused block "H5/$113/SO/H5/& A 7 " (X-XOR2) removed. The signal "H5/$113/SO/& " A 1/2" is unused and has been removed.

The signal "&-A-116" is.unused and has been removed. Unused block "H6/$17" (XOR2) removed. The signal " & A 121" is unused and has been removed. Unused block"i16/$113/S2~/& A 121" (X-XOR2) rernoved. The signal " & A 121/2.0risunused and has been removed. Unused block "H6/$113/S2/& A 121/2.0" (X XOR2) removed.

Unused block "H6/$113/S2/H6/& A 9" (X XOR2) removed. The signal "H6/$113/S2/& A 9/2" is unused and has been removed.

The signal " & A 122" is unused and has beeñ removed. . Unused block "H6/$113/Sl/& A-122" (X-XOR2) removed.

"

The signal " & A 122/2.0ris unused and has been removed. Unused block7HG/$113/S1/& A 122/2.0" (X XOR2) removed.

The signal " & A 122/2.1" is unused and has been removed. Unused block7HG/$113/S1/& A 122/2.1" (X XORZ) removed.

The signal " & A 123" is unused and has been-removed. Unused block "H6/$113/SO/& A 123" (X XOR2) rkmoved. The signal " & A 123/2. O" is unused and has been removed. Unused block "H6/$113/SO/& A 123/2.0" (X XOR2) removed.

Unused block "H6/$113/SO/H6/& A 9" (X XOR2) removed. The signal "H6/$113/SO/& A-9/2" is unused and has been removed.

"

Unused block "H3/$111/$1145" (CY4 42) removea. Unused block "H4/$111/$1145" (CY4-42) removed. Unused block "H5/$111/$1145" (CY4-42) removed. Unused block "H6/$111/$1145" (CY4-42) removed. Unused block "H8/$111/$1145" (CY4-42) - removed.

Optimized Block(s): TYPE BLOCK X XOR2 Hl/$Il/SO/Hl/& A 1 X-XOR2 H~/$I~/s~/H~/&-A 1 X-XOR2 Hl/$Il/S2/Hl/& A I 1 XÑOR2 H1/$113/$11278- X XOR2 Hl/$I13/SO/Hl/&-A-l X-XOR2 Hl/$I13/Sl/Hl/&-A 1 X-XOR2 Hl/$I13/S2/Hl/& A-1 X-XOR2 Hl/$I13/S3/Hl/& A 1 XfOR2 H1/$11/$11271 AND2 H1/$11/$11266 AND2 H1/$11/$11270 X OR2 H1/$11/$11260/H1/$11/$Net00273_/2 X-XOR2 H~o/$II~/so/H~o/& A 13 X-XOR2 H10/$113/S2/HlO/& A 13 X-XOR2 Hl0/$113/S3/H10/& A 13 AND 2 H10/$113/$11234 AND2 H10/$113/$11236 X XOR2 HlO/$I13/Sl/S3ZF<1>/2.0 AÑD2 H8/$113/$11234 AND2 H8/$113/$11236 GND Hl/I from-net-GND

GND HlO/I - from-net-GND vcc Hl/I-from_net-VCC

. o

vcc GND vcc GND vcc GND vcc GN D vcc GND vcc

HlO/I from net VCC H3/I rrom Eet-GND H3/I-from-net-VCC H4/I-fromlnet-GND H4/I-from net-VCC HS/I-fromInet-GND H5 / I-f rom net-VCC HG/I-fromInet-GND HG/I-from net VCC HB/I-from-net-GND H8/I-from-net-VCC - "

To enable printing of redundant blocks removed and signals merged, set the environment variable MAP - REPORT-DETAIL to TRUE and rerun map.

Section 6 - Added Logic """_""""_"""~

Section 7 - Expanded Logic

To enable this section, set the environment variable MAP-REPORT-DETAIL to TRUE and rerun MAP.

"""""""""""""

Section 8 - Signal Cross-Reference

To enable this section, set the environment variable MAP-REPORT-DETAIL to TRUE and rerun MAP.

"""""""""""""""""

Section 9 - Symbol Cross-Reference

To enable this section, set the environment variable MAP REPORT DETAIL to TRUE and rerun MAP.

"""""""""""""""""

- -

Section 10 - IOB

$Net00001 ;=OB) SNet00002- (IOB) SNet00003- (IOB) SNet00004- (IOB) SNet00005- (IOB) SNet00006- (IOB) SNet00007- (IOB) SNet00008- (IOB) SNet00009- (IOB) SNet00010- (IOB) SNet00011- (IOB) SNet00012- (IOB) SNet00013- (IOB) SNet00014- (IOB) SNet00015- (IOB) SNet00016- (IOB) SNet00017- (IOB) SNet00018- (IOB) SNet00019- (IOB) SNet00020- (IOB) SNet00021- (IOB) SNet00022- - (IOB)

""""""""_ Properties

: SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW : SLEW=SLOW

"""""

$Net00023 (IOB) : SLEW=SLOW SNet00024- - (IOB) : SLEW=SLOW

Section 11 - RPMs Hl/$Il/hset Hl/$I13/hset Hl/$IlG/hset Hl/$Ila/hset Hl/$I4/hset Hl/$I8/hset HlO/$Ill/hset HlO/$I13/hset

""""""""-

i l l í l/SI1ó/llset HlO/$Ila/hset HlO/$I3/hset HlO/SIG/hset H3/$Ill/hset H3/SI13/hset H3/SI16/hset H3/$11a/hset H3/$13/hset H3/$IG/hset H4/SIll/hset H4/$113/hset H4/$IlG/hset H4/$118/hset H4/$I3/hset H4/SIG/hset H5/SIll/hset H5/SI13/hset H!i/$Il6/hset H5/$118/hset ~5/SI3/hset H5/SIG/hset HG/$Ill/hset HG/$I13/hset HG/$IlG/hset HG/$IIa/hset HG/SI3/hset HG/SIG/hset Ha/$Ill/hset H8/$I13/hset Ha/SIlG/hset Ha/$I18/hset ~a/$I3/hset ~a/$IG/hset

2 2 5 8 8 6 - 4 cornps - 4 cornps - 4 cornps - 4 cornps - 4 cornps - 4 cornps - 4 cornps - 4 cornps - 4 colnp;; - 4 cornps - 4 cornps - 4 cornps - 3 cornps - 4 cornps - 4 cornps - 4 cornps - 4 cornps - 4 cornps - 3 cornps - 4 cornps - 4 cornps - 4 cornps - 4 cornps - 4 cornps - 3 cornps - 4 cornps - 4 cornps - 4 cornps - 4 comps - 4 cornps - 3 cornps - 4 cornps - 4 cornps - 4 cornps - 4 comps - 4 comps - 3 cornps - 4 cornps - 4 cornps - 4 cornps - 4 cornps - 4 cornps

Section 12 - Guide Report

Guide not run on this design. ~""""""~"""~""

Disposicih & Trazado

La disposición y el trazado, se realiza de manera automática, existe una herramienta que crea un mapa del diseño lógico dentro del FPGA con el encaminamiento correcto, es decir que el diseñador no tiene necesidad de identificar cuales CLBs y cuantos debe contener el diseño, ni la interconexión de estos con los IOBs.

El diseño en bloques funcionales, permite la optimización, ya que estos permiten el acceso y manipulación cuando se presentan problemas en la etapa de trazado.

Este reporte muestra el número de dispositivos utilizados, además inQca el tiempo de colocación que fue de 24seg, el tiempo de optimización del diseño 25seg y también muestra el tiempo en que se llevo a cabo el encaminamiento.

Reporte de retardos

Retardo promedo de conexión en el diseño 3.273ns. Retardo promedio en las 10 peores redes 10.76511s. Retardo máximo de pata 12.17511s.

El reporte indica también el número que corresponde a las patas de las entradas, salidas, tierra y Vcc en el circuito.

20

PAR: Xilinx Place And Route M1.5.19. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved.

Sun Mar 26 15:45:12 2000

par "w -01 2 -d O map.ncd emma.ncd emma.pcf

Constraints file: emma.pcf

Loading device database for application par from file "map.ncd".

Loading device for application par from file '4013e.nph' in environment c: : i fndtn. Device speed data version: x1 - 0.14 1.6 PRELIMINARY.

"emma" i s an NCD, version 2.27, device xcs30, package vq100, speed -3

Device utilization summary:

Number of External IOBs Flops : Latches:

Number of CLBs Total CLB Flops: 4 input LUTs: 3 input LUTs:

48 out of 77 62% O O

179 out of 576 31% O out of 1152 1%

214 out of 1152 18% 3 out of 576 1%

Overall effort level (-01): 2 (set by user) Placer effort level (-pl) : 2 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (default)

Starting initial Placement phase. REAL time: 7 secs Finished initial Placement phase. REAL time: 7 secs

Starting Constructive Placer. REAL time: 8 secs Placer score = 164912 Placer score = 148326 Placer score = 134772 Placer score = 122412 Placer score = 121438 Placer score = 112204 Placer score = 101456 Placer score = 100324 Placer score = 97690 Placer score = 94562 Placer score = 91260 Placer score = 89580 Placer score = 88144 Placer score = 86878 Placer score = 86338 Placer score = 86160 Placer score = 86100 Placer score = 86096 Placer score = 82736 Placer score = 82264 Placer score = 81784

Placer score = E1424 Placer score = 81304 Placer score = 81186 Placer score = 81006 Placer score = 79746 Placer score = 79438 Finished Constructive Placer. REAL time: 24 SecS

Writing design to file "emma.ncd".

Starting Optimizing Placer. REAL time: 24 secs Optimizing Swapped 8 comps. Xilinx Flacer [l] 7919E REAL time: 2 5 sezs

Finished Optimizing Placer. REAL time: 25 secs


Total REAL time to Placer completion: 25 secs Total CPU time to Placer completion: O secs

O connection(s) routed; 651 unrouted active, 92 unrouted PWR/GND. Starting router resource preassignment Completed router resource preassignment. REAL time: 26 s'ecs Starting iterative routing. Routing active signals. End of iteration 1 651 successful; O unrouted active,

End of iteration 2 651 successful; O unrouted active,

Constraints are met. Routing PWR/GND nets. Routing active and PWR/GND signals. End of iteration 3 743 successful; O unrouted; (O) REAL time: 37 secs Constraints are met. Power and ground nets completely routed. Writing design to file "emma.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 743 successful; O unrouted; (O) REAL time: 58 secs Writing design to file "emma.ncd". Total REAL time: 58 secs Total CPU time: 0 secs End of route. 743 routed (100.00%); O unrouted. No errors found. Completely routed.

This design was run without timing constraints. It is likely that much

92 unrouted PWR/GND; (O) REAL time: 29 secs

92 unrouted PWR/GND; (O) REAL time: 29 secs

Total REAL time to Router completion: 58 secs Total CPU time to Router completion: O secs

Generating PAR statistics.

The Delay Summary Report

The Score for this design is: 542

The Number of signals not completely routed for this design is: O

The Average Connection Delay for this design is: 3 . 2 1 3 ns The hverage Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design i s : 0.000 ns The Maximum Pin Delay is: 12.175 ns The Average Connection Delay on the 10 Worst Nets is: 10.165 ns

Listing Pin Delays by value: (ns)

d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 """-" "_""" --------- - - - - - - - - - _"""" """"-

719 24 O O O O


All signals are completely routed

Total REAL time to PAR completion: 59 secs Total CPU time to PAR completion: O secs

PAR done.

PAR: Xilinx Place And Route M1.5.19. Copyright (c) 1995-1998 Xilinx, Inc. A l l rights reserved. Sun Mar 26 15:46:11 2000

Xilinx PAD Specification File . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input file: map. ncd Output file : emma. ncd Part type: xcs30 Speed grade: -3 Package : v q l 0 0

Pinout by Pin Name: +"""""""""""""""~""""""""~~"""""-

+"""""""+

I Pin Name I Direction I Pin Number I +""""""""""""""""~"""""""~~----------- +""""""" t

$Net00001 -

$Net00002 -

$Net00003 -

$Net00004 -

$Net00005 - I I $Net00006 I I $Net00007 - I I $Net00008 I I $Net00009 - I I $Net00010 I I $Net00011 - I I $Net00012 -

-

-

-

I I I I I I I I I I I I I I I I

$Net00013 -

$Net00014 -

$Net00015 -

$Net00016 -

SNet00017-

$Net00018 -

$Net00019 -

$Net00020 -

I OUTPUT

I OUTPUT

I OUTPUT

1 OUTPUT

I OUTPUT

I OUTPUT

I OUTPUT

I OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

1 OUTPUT

I OUTPUT

I OUTPUT

I OUTPUT

I OUTPUT

1 OUTPUT

I OUTPUT

I OUTPUT

P9

P8

P6

P19

I P33

I P18

1 P30

I P10

I

I

I

I

I

I

I

I

I

I

I

I

P2 1

P27

P2 o P2 9

P17

P28

P16

P14

P32

P31

P34

P35

I I $ N e t 0 0 0 2 1 I I $ N e t 0 0 0 2 2 - I I $ N e t 0 0 0 2 3 I

-

-

$ N e t 0 0 0 2 4 -

$ N e t 0 0 2 1 4 -

$ N e t 0 0 2 1 5 -

S N e t 0 0 2 i Ó -

$ N e t 0 0 2 1 7 I

-

I $ N e t 0 0 2 1 8 - I I $ N e t 0 0 2 1 9 I I $ N e t 0 0 2 2 0

-

I I I I I I I I I I S N e t 0 0 2 2 5 - I I $ N e t 0 0 2 2 6 I I $ N e t 0 0 2 2 7 - I

-

S N e t 0 0 2 2 8 -

$ N e t 0 0 2 2 9 -

$ N e t 0 0 2 3 0 -

S N e t 0 0 2 3 1 -

SNet00232-

S N e t 0 0 2 3 3 -

S N e t 0 0 2 3 4 -

S N e t 0 0 2 3 5 -

S N e t 0 0 2 3 6 - I I S N e t 0 0 2 3 7 - I

$ N e t 0 0 2 2 1 -

$ N e t 0 0 2 2 2 -

S N e t 0 0 2 2 3 -

$ N e t 0 0 2 2 4 -

I OUTPUT

I OUTPUT

I OUTPUT

I OUTPUT

I INPUT

I INPUT

j IiJBUT

I INPUT

I INPUT

I INPUT

I INPUT

1 INPUT

I INPUT

I INPUT

I INPUT

I INPUT

I INPUT

I INPUT

I INPUT

I INPUT

1 INPUT

I INPUT

I INPUT

I INPUT

I INPUT

I INPUT

I INPUT

I INPUT

+""""""""""""""""""""""""+"""""- +""""""" +

I Dedicated o r S p e c i a l Pin Name Number I

I P15

I P 9 7

I P 1 3

P7

P 6 1

P 5 4

F4 2

I P 4 5

I P 5 7

I P 6 6

I P 6 2

P 8 5

P4 3

P 8 4

P 9 1

I P 8 7

I P 9 2

I P 9 0

I P 8 3

I P 8 6

I P 6 5

I P 5 8

P60

P 5 9

P4 4

P4 6

P 5 5

1 P 5 6

I Pin

f""""""""""""""""""""""""""""""

+""""""" + I /PROG 1 P52 I I CCLK I P74 I I DONE I P50 I I GND I P38 I 1 GND I I I GND I P77 I 1 GND I P49 I I GND I P23 I I GND I P88 I I GND I P64 I I GND I P11 I

I

I

I

I

I

I

I

I

I vcc 1 P51

I vcc I P12

I vcc I P37

I vcc 1 PlOO

I vcc I P89

I vcc I P75

I vcc 1 P63

I vcc I P25

+""""""""""""""""""""""""""""""

+"""""""+

Pinout by Pin Number: +"""""""+"""""""""""""""""-+""------- +"""""" +

I Pin Number I Pin Name I Direction 1 Constraint I +"""""""+"""""--""""""""""""-+"--------- +"""""" +

I p1 I GND I I

I P2 I I I I

P3

P4

P5

P6 $Net00003 -

I I

I I

I I

I OUTPUT I

I I P17 I

I 1 P19 I I P20 I I P21 I I P23 I 1 P25 I I P27 I 1 P28 I I P29 I I P30 I I P31 I I P32 I I P33 I I P34 I I P35 I I P36 I I P37 I I ~ 3 a I I P39 I

I p1a

I $Net00024 -

1 $Net00002 -

1 $Net00001 -

I $Net00008 -

1 GND

1 vcc

I $NetOCC2S -

1 $Net00016 -

I $Net00021 -

I $Net00015 -

I $Net00013 -

I $Net00006 -

1 $Net00004_

1 $Net00011 -

1 $Net00009 -

I GND

I vcc

I $Net00010-

1 $Net00014-

I $Net00012_

I $Net00007 -

I $Net00018-

I $Net00017 -

1 $Net00005-

I $Net00019-

I $Net00020-

I

I vcc

1 GND

I

I OUTPUT

I OUTPUT

1 OUTPUT

I OUTPUT

I

I

1 3UTP'JT

I OUTPUT

I OUTPUT

I OUTPUT

I OUTPUT

I OUTPUT

1 OUTPUT

I OUTPUT

I OUTPUT

I

I

1 OUTPUT

I OUTPUT

I OUTPUT

I OUTPUT

I OUTPUT

1 OUTPUT

I OUTPUT

I OUTPUT

1 OUTPUT

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I P 4 0 I I P 4 1 I I P 4 2 I I P 4 3 I I P 4 4 I I P 4 5 I I P 4 6 I I P 4 7 I I P 4 8 I I P 4 9

. I 1 P 5 0 I I P 5 1 I I P 5 2 I I P 5 3 I I P 5 4 I I P 5 5 I I P 5 6 I I P 5 7 I I P 5 8 I I P59 I I P 6 0 I I P 6 1 I I P 6 2 I I P 6 3 I 1 P 6 4 I I P 6 5 I I P66 I I P 6 7 I I P 6 8 I I P 6 9 I I P 7 0

t

I $ N e t 0 0 2 1 6 -

I $ N e t 0 0 2 2 2 -

I $ N e t 0 0 2 3 4 -

I $ N e t 0 0 2 1 7 -

I $ N e t 0 0 2 3 5 -

I

I GND

I DONE

I vcc

I /PROG

I

I S N e t 0 0 2 1 5 -

I $ N e t 0 0 2 3 6 -

I $ N e t 0 0 2 3 7 -

I $ N e t 0 0 2 1 8 -

I $ N e t 0 0 2 3 1 -

I $ N e t 0 0 2 3 3 -

I $ N e t 0 0 2 3 2 -

I $ N e t 0 0 2 1 4 -

I $ N e t 0 0 2 2 0 -

I vcc

I GND

I $ N e t 0 0 2 3 0 -

I $ N e t 0 0 2 1 9 -

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

I I P 7 1 I I P72 I I P73 I I P74 I I P75 I I P77 I i 276 I I P79 I I P80 I I P 8 1 I I P82 I I P83 I I P84 I I P85 I 1 P86 I 1 P87 I I P88 I I P89 I I P90 I I P91 I I P92 I 1 P93 I

I

I

I

I CCLK

I vcc

I GND

I

I

I

I

I

I SNet00228-

I SNet00223-

I SNet00221-

I SNet00229-

I $ N e t 0 0 2 2 5 -

I GND

I vcc

I $Net00227 -

I $Net00224 -

I $ N e t 0 0 2 2 6 -

I

P94

P95

P96

P97

P98 I I P99 I I PlOO I

I

I

I

I

I

I

' I

I

I

I

I

I INPUT

I INPUT

1 INPUT

I INPUT

I INPUT

I

I

I INPUT

I INPUT

1 INPUT

I

I

I

I

$Net00022 - I OUTPUT

I

I

I vcc

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

+"""""""+"""~""""""""""""-"-+----------- +"""""" +

# # Pinout constraints listing # These constraints are in PCF grammar format # and may be cut and pasted into the PCF file 2 2 5 8 8 6 # after the "SCHEMATIC END ;" statement to # preserve this pinout for future design iterations. # COMP "$Net00001 LOCATE = SITE "P9" ; COMP "$Net00002-" LOCATE = SITE ''P8" ; COMP "$Net00003-" LOCATE = SITE "P6" ; COMP "$Net00004-" LOCATE = SITE "P19" ; COMP "$Net00005-" - LOCATE = SITE "P33" ; COMP "$NeiOGOü6 'I LOCATE = SIT6 " P i S " ; COMP "$Net00007-" LOCATE = SITE "P30" ; COMP "$Net00008-" LOCATE = SITE "P10" ; COMP "$Net00009-" LOCATE = SITE "P21" ; COMP "$Net00010-" LOCATE = SITE "P27" ; COMP "$Net00011-" LOCATE = SITE "P20" ; COMP "$Net00012-" LOCATE = SITE "P29" ; COMP "$Net00013-" LOCATE = SITE "P17" ; COMP "$Net00014-" LOCATE = SITE "P28" ; COMP "$Net00015-" LOCATE = SITE "P16" ; COMP "$Net00016-" LOCATE = SITE "P14" ; COMP "$Net00017-" LOCATE = SITE "P32" ; COMP "$Net00018-" LOCATE = SITE "P31" ; COMP "$NetUU019-" LOCATE = SITE "P34" ; COMP "$Net00020-" LOCATE = SITE "P35" ; COMP "$Net00021-" LOCATE = SITE "P15" ; COMP "$Net00022-" LOCATE = SITE l'P97" ; COMP "$Net00023-" LOCATE = SITE I'P13" ; COMP "$Net00024-" LOCATE = SITE "P7" ; COMP "$Net00214-" LOCATE = SITE 'lP61" ; COMP "$Net00215-" LOCATE = SITE "P54" ; COMP "$Net00216-" LOCATE = SITE "P4.2" ; COMP "$Net00217-" LOCATE = SITE "P45" ; COMP "$Net00218-" LOCATE = SITE "P57" ; COMP "$Net00219-" LOCATE = SITE "P66" ; COMP "$Net00220-" LOCATE = SITE "P62" ; COMP "$Net00221-" LOCATE = SITE "P85" ; COMP "$Net00222-" LOCATE = SITE "P43" ; COMP "SNet00223"" LOCATE = SITE "P84" ; COMP "$Net00224-" LOCATE = SITE "P91" ; COMP "$Net00225-" LOCATE = SITE "P87" ; COMP "$Net00226-" LOCATE = SITE "P92" ; COMP "$Net00227-" LOCATE = SITE "P90" ; COMP "$Net00228-" LOCATE = SITE "P83" ; COMP "$Net00229-" LOCATE = SITE "P86" ; COMP "$Net00230-" LOCATE = SITE "P65" ; COMP "$Net00231-" LOCATE = SITE "P58" ; COMP "$Net00232-" LOCATE = SITE "P60" ; COMP "$Net00233-" LOCATE = SITE 'lP59" ; COMP "$Net00234-" LOCATE = SITE "P44" ; COMP "$Net00235-" LOCATE = SITE "P46" ; COMP "$Net00236-" LOCATE = SITE "P55" ; COMP "$Net00237I" LOCATE = SITE "P56" ; #

Sun Mar 2 6 1 5 : 4 6 : 1 0 2 0 0 0

F i l e : e m m a . d l y

The 2 0 Worst Net D e l a y s are: """""""""""""~""

I Max D e l a y ( n s ) I Netname I """""""""""""""~

1 2 . 1 7 5 1 1 . 9 6 2 1 1 . 4 7 6 1 1 . 2 3 2 1 1 . 2 0 4 1 0 . 7 4 1 1 0 . 4 2 4 1 0 . 2 3 0

9 . 5 7 0 9 . 3 2 5 9 . 1 4 2 9 . 0 7 5 9 . 0 6 1 8 . 9 4 6 8 . 8 1 8

& A 140 & A 90 E3X<2> & A 5 9 & A 68 H 8 / $ K t 0 0 0 6 5 -

"

"

"

H%/$ÑetOO065- & A 3 1 & A 5 1 & A 1 2 6 S3Y<3>

"

"

"

8.159 E3Y<2> 8.057 E3Y<3> 7 .278 E3Y<5> 7 . 1 0 5 & A-65 7 . 0 4 2 E=F<3> """"""_""""""""""

....................................

"""_ Net D e l a y s

.....................................

& A 100 "

& A 100.X "

1 . 8 5 3 & . A 1 3 7 . F 2 4 . 1 4 7 & A 1 2 5 . F 1 "

"

& A 101 "

& A 102 .Y "

6 . 8 0 7 & A 139 .G1 4 . 9 5 3 & A 127.G4

& A 1 0 2 "

&- A - 102.X 5 . 1 3 7 & A 1 3 9 . F 2 4 .124 & A 1 2 7 . F 1

& A 1 0 3 "

& A 104 .Y "

5 .171 H6 /$Ne t00118- 2 . 8 1 3 & A 129.G3- "

& A 104 "

& A 104.X

F1

"

5 . 7 8 3 & A 1 2 9 . F 1 --

& A 1 0 5 "

& A 106.Y "

4.214 & A 131.G4 "

& A 106 "

& A 106.X "

6.157 & A 131.F1

& A 107 "

& A 107.X "

1.836 H6/$Net00118 .F2 1.836 & A 129.~4- 1.836 &-AP133.G3 1.836 H6/$Net00104-.G2

& A 108 "

& A 108.X -- 1.851 & A 129.F2 2.412 &-A-133.F1 "

& A 109 "

& A ll0.Y "

4.896 & A 131.G1 5.037 &A-135.G4

& A 110 "

& A ll0.X "

4.266 &-A-131.F2 2.263 & A 135.F1 "

& A 111 "

& A 112.Y "

6.266 H6/$Net0006OP.F1 5.956 & A 137.G3- "

& A 112 "

& A 1 1 2 . X "

5.810 & A 137.F1 "

& A 113 "

& A 114.Y "

3.420 & A '139.G4

& A 114 "

& A 114.X "

4.120 & A 139:Fl

& A 115 "

& A 115.X "

9.325 & A 35.F3 9.325 &A-35.G3 9.258 &-A-33. F1 9.325 H8/$Kt00127 .F1 6.171 H8/$113/$119?.F3 6.171 H8/$Net00065-.F3 1.358 H8/$116/$1195.F1 7.802 H8/$Net00060-.F2 6.171 & A 20.G1 8.131 &-A-20.F3 8.307 & A 22.G3 8.307 & A 22. F3 4.835 H8/$Net00104_.Gl

"

4.680 &-A-16.G1 5.168 & A 16.F3 5.058 &-A-18. G3 5.058 &-A-18. -- F3

& A 117 "

& A 117.X "

1.833 & A 115.C3 "

& A 119 "

& A 119.X "

4.352 & A 35.G4

L A 124 "

& A 124.X "

2.733 H8/$Net00120 .G2 4.404 & A 24.G3 3.044 & A 20.F2

- "

"

& A 125 "

& A 125.X "

1.487 L A 22.G1 2.273 &-A-24.F1 "

& A 126 "

& A 127.Y "

1.346 & A 22.k2 8.946 & A 26.G4

L A 121 "

& A 127 .X "

2.164 L A 26.F1

& A 128 "

& A 129.Y "

1.371 H8/$Net00118_.Fl 1.404 & A 28.G3

-

"

& A 129 "

& A 129.X "

1.173 & A 28.F1 "

& A 130 "

& A 131.Y "

1.067 & A 30.G4 "

& A 131 "

& A 131.X "

1.173 L A 30.F1 "

& A 132 "

& A 132.X "

2.952 H8/$Net00104-.G2

2.780 2.471

& A 133 "

& A 133.X 2.063 "

2.388

& A 134 "

& A 135.Y 1.592 2.512

- _

& A 135 "

& A 135.X 1.149 "

& A 136 "

& A 137.Y 2.366 "

1.846

& A 137 "

& A 137.X 2.776 "

& A 138 -- & A 139.Y "

2.249

& A 139 "

& A 139.X l. 708 "

& A 140 "

& A 140.X 2.113 "

2.113 2.278 3.771 3.925 2.568 2.568 2.568 10.650 12.175 11.158 12.175 12.175 12.175 11.158 11.158 12.175 12.175 12.175

& A 142 "

& A 142.X 2.230 "

& A 16.G3 "

& A 2 8 . ~ 2 "

& A 30.G1 & A 16.F1 "

"

& A 30.72 & A 18.G4 "

"

& A 18.F1 "

H8/$Net00060 - . F1 & A 20 .G3 "

& A 20.F1 "

& A 22 .G4 "

& A 22.F1 "

& A 44.F3 & A 44.G3 & A 42.F1 H3/$Kt00127 .F2 & A 46.G1 & A 46.F3 & A 48.G3 & A 48.F3 H3/$Kt00065 .F1 H3/$Net00060-.F3 & A 62.Gl & A 62.F3 & A 64 .G3 & A 64.F3 H3/$Net00104 - .G1 & A 58.G1 & A 58 .F3 & A 60.G3 & A 60.F3

"

"

- "

"

"

- "

"

- _

"

"

"

"

& A 42.F2 "

& A 143 "

& A 144.Y "

2.183 & A 44.G4 "

& A 144 "

& A 144.X - _ 1.701 & A 44.F1 "

& A 145 "

& A 146.Y "

1.813 H3/SNet00127 .F1 1.827 & A 46.G3

-

"

"

2.114

& A 147 "

& A 148.Y 2.905 "

& A 148 "

& A 148.X 1.635

- _

& A 149 "

& A 149.X 1.447 "

1.646 1.812

& A 15 "

& A 15.X "

1.592 l. 573 1.433

& A 150 "

& A 150.X 1.809 "

1.427

& A 46.F1 "

& A 48.G4 "

& A 48.F1 "

H3/$Net00120 .G2 & A 50.G3 & A 58 .F2

- - - "

HlO/$NetO0104 .G2 S3X<6> .G3 S3Y<O>. G1

-

& A 60.G1 & A 50.F1 "

"

& A 1 5 1 "

& A 152.Y "

.2.119 & A 60.F2 1.715 &-A-52.G4 "

& A 1 5 1 "

& A 152.Y "

.2.119 & A 60.F2 1.715 &-A-52.G4 "

& A 152 "

&-A 152.x - 1.889 H3/$Net00060 .F2 1.889 & A 62.G4 1.649 &A-52.F1

-

"

& A 153 - _ & A 154.Y "

4.372 H3/$Net00118 .F1 3.865 & A 54 .G3 3.012 & A 62.F2

- "

--

& A 154 "

h A 154.X "

3.610 & A 54.F1 "

1.358 & A 64.G1 "

& A 155 "

& A 156.Y "

2.966 & A 56.G4 4.287 & A 64 .F2 "

"

& A 156 "

& A 156.X "

1.708 & A 5 6 . F l "

& A 157 "

& A 157.X "

2.743 E3/SNet@!l104 .G2 4.455 & A 58.G3 4.600 &-A-50.F2 "

-

& A 158 - _ & A 158.X "

4.034 & A 58.F1 4.472 & A 52.G1 "

"

& A 159 "

& A 160.Y "

1.979 & A 60.G4 1.857 &-A-52. F2 "

& A 16 "

& A 16.X "

2.938 S3Y<O>. F2 3.994 S3X<6>. F1

& A 160 "

& A 160.X "

3.305 H3/$Net00118 .F2 3.305 & A 54.G4 3.995 &A-60.F1

-

"

& A 161 "

& A 162.Y "

2.806 H3/$Net00060 .F1 2.406 & A 62.G3 2.796 &-A-54.F2

-

"

& A 162 "

& A 162.X "

1.835 & A 56.G1 1.837 & A 62.F1 "

"

& A 163 "

& A 164.Y "

1.829 & A 56.F2 1.491 &-A-64.G4 "

& A 164 "

& A 164.X "

1.708 & A 64.F1 "

& A 17 "

& A 18.Y "

1.305 S3X<4>.G4

& A 18 "

& A 18.X "

l. 317 S3X<4>. F1

& A 20.Y "

2.328 HlO/$Net00060 .F1 1.983 S3X<2>. G3

-

& A 20 "

& A 20.X "

2.613 S3X<2>. F1

& A 21 "

& A 22.Y "

1.777 S3X<O>. G4

& A 22 "

& A 22.X "

2.800 S3X<O>.F1

& A 23 "

& A 23.X "

2:989 HlO/$NetO0120 .G2 4.34 9 S3Y<6> .G3 4.34 9 S3X<O>. G1

-

& A 24 "

& A 24.X -- 1.067 S3X<O>. F2 3.872 S3Y<6>. F1

& A 25 "

& A 26.Y "

1.395 S3Y<4>.G4

& A 26 "

& A 26.X "

3.570 S3Y<4>.F1

& A 27 "

& A 28.Y "

4.213 HlO/SNet00118 .F1 4.022 S3Y<2>.G3

-

& A 28 "

& A 28.X "

3.570 S3Y<2>. F1

& A 29 - _ & A 30.Y "

2.853 S3Y<O>.G4

&, A 30 "

& A 30.X "

3.570 S 3 Y < O > . F1

& A 31 - _ & A 115.Y "

7.714 S3ZF<4>.F3

7.714 7.714 6.236 6.236 6.236 6.236 4.756 4.540 4.540 4.388 8.235 9.075 8.090 7.846 7.846 5.985 5.985 4.756 4.540 4.540

& A 33 "

& A 33.X "

2.923 1.344

& A 35 "

& A 35.X "

2.471

& A 40 "

& A 140.Y 2.280 "

2.280 6.115 4.838 3.138 5.288 5.572 5.572 7.846 7.179 4.966 7.293 7.628 7.628 8.784 8.784 10.230 10.230 10.230

& A 42 "

~~

& A 42.X "

10.424

S3ZF<4>. G3 S3ZF<6>. F3 S3ZF<6>. G1 HlO/$Net00054 .G1 HlO/$Net00127-.Fl - S3ZF<2>.G1 S3ZF<2>. F3 S3ZF<O>.G3 S3ZF<O>. F3 HlO/$Net00065 .F1 HlO/$Net00060-. F2 S3X<2>. G1 S3X<2>. F3 S3X<O> .G3 S3X<O>. F3. H10/$Net00104 .G1 S3X<6>. G1 S3X<6>. F3 S3X<4>.G3 S3X<4>. F3

-

-

S3ZF<6>. F1

& A 69.F3 & A 69.G3 & A 67.F1

"

"

H4/$Kt00127 .F2 & A ' 71.G1 & A 71.F3 H4/$Kt00065 .G3 H4/$Net00065-.F3

- "

& A 65.F1 H4/$Net00060 . F3

-

& A 87.G1 & A 87.F3 & A 89.G3 & A 89.F3 H4/$Net0010 & A 83.G1 & A 83.F3

A 85.G3 & A 85.F3

"

"

"

"

"

&- - "

&" - A 65. F2

-

4 .G1 -

& A 43 "

& A 44 "

& A 44.X ~ ..

"

1.413 & A 69.G4

& A 45 "

& A 46.Y "

1.756 & A 69.F1 "

1.106 & A 71.G3 -

"

& A 47 -- & A 48.Y "

1.457 & A 71.F1 "

& A 48

& A 49 "

& A 49.X ~ ~.

"

1.918 H4/$Net00120 .G2 2.166 & A 75.G3 2.353 &A-85.G1

-

"

& A 50 "

& A 50.X "

2.125 & A 85.F2 2.263 &-A-75.F1 "

& A 51 "

& A 52.Y - _ 9.061 H4/$Net00060 .F2 9.061 & A 87.G4 2.303 &-A-77.G4

-

"

& A 52 "

& A 52.X "

5.565 & A 87.F2 4.303 &-A-77.F1 "

& A 5 3 "

& A 54.Y ~-

"

2.177 H4/$Net00118 .F1 1.978 & A 79.G3 2.321 &-A-89.G1

-

"

"

& A 55 "

& A 56.Y "

2.303 & A 81.G4 "

& A 56 "

& A 56.X "

3.525

& A 57 "

& A 57.X "

1.512 1.860 2.312

& A 58 "

A 5a.x "

4.254 1.635

& A 59 "

& A 60.Y "

11.232 9.F 2 . 6 2

& A 60 "

& A 60.X "

5.789 3.796

& A 61 "

& A 62.Y "

4.084 3.894 4.084

& A 62

4.411

& A 63 "

& A 64.Y "

2.830

& A 64 "

& A 64.X "

4.144

& A 65 "

& A 65.X "

6.613 6.673 7.105 6.199

& A 81.F1 "

H4/$Net00104 .G2 & A 53.G3 & A 77 .G1

- "

"

& A 53. F1 T ?, ?7.F2 "

"

H4/$Net00118 - . F2 & A 79.G4 & A 85.G4 "

"

& A 79.F2 & A 85.F1 - _ "

H4/$Net00060 .F1 & A 87.G3 & A 81.G1

- - _ "

& A 81.F2 & A 87.F1 "

"

& A 89.G4 "

& A 89.F1 "

& A 94.F3 & A 94 .G3 & A 92.F1 H5/$Kt00127

"

"

. F2 6.873 & A 96.G1 3.728 & A 96.F3

- "

3.728 H5/$Kt00065 .F3 1.331 H5/$116/$1195.F1 3.021 H5/$Net00060 .F3 3.286 & A 112.G1- 3.021 &-A-li2.F3 3.021 & A 114.G3 3.021 &-A-114.F3

"

3.728 H5/$Net00104 .G1 ~ ~~

-

3.728 & A 108.G1 3.286 &A-108.F3 3.286 &-A-llO.G3 3.286 &-A-llO.F3

~~

"

& A 67 "

& A 68 "

& A 69.Y "

11.204 & A 92.F2 "

& A 69

& A 70 "

& A 11.Y "

2.806 & A 94.F1 "

1.828 & A 96.G3 -

"

& A 72 "

H4/$Net00065 .Y 2.213 -& A 96.Fl

& A 74 "

& A 74.X ~~

"

1.378 HS/$Net00120 .G2 4.332 & A 100.G3- 6.146 &-A-llO.F2 "

& A 75 "

& A 75.X "

1.699 H5/$Net00060 .F2 2.967 & A 112.G4- 2.085 &-A-lOO.Fl - _

& A 7 6 "

& A 17.Y "

1.499 & A 112.F2 1.806 &-A-102.G4 - _

& A 71 "

& A 77.X "

1.576 & A 114.G1 2.249 & A 102.F1 "

"

& A 78 "

& A 79.Y "

1.248 H5/SNetC0118 .F1 1.726 & A 104.G3- 1.998 & A 114.F2 "

"

& A 79 "

& A 79.X "

1.173 & A 104.F1 "

& A 80 "

& A 81.Y "

1.067 & A 106;G4 "

& A a 1 "

& A 81.X ~-

"

1.173 & A 106.F1 "

& A 82 -- & A 82.X "

2.791 H5/$Net00104 .G2 2.374 & " A 108.G3- 2.479 G A lC2.FZ "

& A 83 "

.s A a3.x ~-

"

3.510 H5/$Net00118 .F2 3.510 & A 104.G4- 4.805 & A 108.F1 "

"

& A 84 "

& A a5.y "

3.331 & A 104.F2 2.296 &-A-llO.G4 "

& A a 5 "

& A 85.X "

1.777 & A 106,Gl 2.333 & A llO.F1 "

"

& A 86 "

& A 87.Y "

4.362 H5/$Net00060 .F1 2.602 & A 112.G3- 3.548 & A 106.F2 "

"

& A 8 7 "

& A 81.X "

3.215 & A 112.F1 --

& A aa "

& A 89.Y "

3.145 & A 114.G4 "

& A 89 "

& A 89.X "

1.635 & A 114.F1 "

& A 90 "

& A 65.Y "

11.962 & A 119.F3 11.962 &-A-119.G3 9.190 &-A-117.F1 7.128 H6/$Kt00127 .F2

11.117 & A 120.G1- 6.824 & A 120. F3 "

~~

6.824 H6/$Kt00065 .F3 5.911 & A 115.F1- 9.190 H6/$Net00060 .F3

10.892 & A 137.G1- - _

9.190 & A 137.F3

7.322 &-A-139.F3 7.927 H6/$Net00104 .G1 7.811 & A 133.G1-

7.322 &-A-139.G3

5.595 &-A-133.F3 5.595 &-A-135.G3 5.595 &-A-135. F3

~.

"

& A 92

& A 95

& A 96 "

& A 96.X - _ l. 397 H6/$Net00127 . F1 1.367 & A 120.G3- "

& A 99 "

& A 99.X "

4.024 H6/$Net00060 .F2 5.536 & A 137.G4- 5.551 &-A-125.G3 4.024 H6/$%t00120 .G2

-

E3X<O> $Net00237 .I2

3.804 & A 156.F2 5.224 & A . 164.F1

- _ --

E3X<1> $Net00236 .I2

4.233 & A 156,Gl 5.141 &-A-164.G4 "

E3X<2> $Net00235 .I2

11.416 & A 154.F2 10.162 &-A-162.F1 "

E3X<3> $Net00234 .I1

3.769 Hl/$Net00107 .F2 2.441 & A 154.G3- 3.951 & A 162.G1 3.951 H1/$Et00127 .F1

"

-

E3X<4> $Net00233 .I2 -

5.055 & A :52.F2 4.913 &-A-160. F1 "

E3X<5> $Net00232 .I2

6.861 & A 152.G1 6.477 & A 160.G4 "

"

E3X<6> $Net00231 .I1

2.382 & A 150iF2 4.472 & A 158.F1 "

- _

E3X<7> $Net00230 .I1

5.137 Hl/$Net00124 .G1 3.013 & A 150.G3- 3.013 &-A-158.G1 2.863 H1/$Gt00140 .G2 -

E3Y<0> $Net00222 .I2

5.012 & A 1 5 6 . ~ 1 "

5.224 & A 164.F2 "

E3Y<1> $Net00215 .I2

6.684 & A 156.G4 5.254 & A 164 .G1 "

"

E3Y<2> $Net00216 .I2

7.147 & A 154.F1 8.159 &-A-162.F2 "

E3Y<3> $Net00217 .I1

7.072 Hl/SNet00107 .F1 7.042 & A 154.G1- 7.023 &-A-162.G3 8.057 H1/$Kt00127 .F2

~-

E3Y<4> $Net00218 .I2

4.784 & A 152.F1 2.772 &-A-160.F2 "

E3Y<5> $Net00219 .I2

7.278 & A 152.G4 5.164 & A 160.G1 "

--

E3Y<6> $Net00220 .I2

5.659 & A 150.F1 6.170 &-AP158.F2 "

E3Y<7> $Net00214 .I1

2.810 Hl/$Net00124 .G2 4.431 & A 150.G1- "

4.431 & A 158:G3 4.134 H1/$Gt00140 .G1 -

E3ZF<O> $Net00221 .I2

3.269 & " A 148.F1

E3ZF<1> $Net00223 .I2

4.137 & A 148.G4 "

E3ZF<2> $Net00229 . I1

1.8i4 c A 146.~1 "

E3ZF<3> $Net00228 .I1

7.042 Hl/$Net00080 .F1 7.042 & " A 146.G1-

E3ZF<4> $Net00226 .I1

1.390 & " A 144.F1

E3ZF<5> $Net00227 .I2

1.830 & " A 144.G4

E3ZF<6> $Net00224 .I1

1.314 & " A 142.~1

E3ZF<7> $Net00225 .I2

2.121 2.276 1.407

GLOBAL LOGICO PWR-GND - 3.12

3T5 8 2

GLOBAL LOGICO-O PWR-GND 32.y -

IT1 3 4 1.381 1.134 1.217

GLOBAL LOGICO 1 PWR-GND - 3 7 T ~

1T12 5 1.197 1.341 1.197

Hl/SNet00097 .G1 & " A 142.G1- & A 140.F4 "

S3Y<2>. F2

S3ZF<2>. F2 S3ZF<2>.F1 S3ZF<O>.G4 S3ZF<O>. F1

S3ZF<6>. F2 S3ZF<4>.Gl S3ZF<4>. F2 S3ZF<4>. F1

GLOBAL LOGICO 10 PWR-GND - 213.12

5,098 H5/$Net00065 .G4 3.673 H5/$Net00065-.Gl 5.098 H5/$Net00065-.F2 -

3.673 H5/$Net00065 . F1 -

GLOBAL LOGICO 11 PWR-GND - 2 1 9 . ~

17107 & -- A 108.F2 1.084 & A llO.Gl - _


1T067 & A 69. F2 "


IT035 81/$118/$1195.?1

GLOBAL LOGICO 14 PWR-GND - 23-8.~

1,394 & A 71.F2 1.240 H4/$Net00065-.Gl 1.394 H4/$Net00065 .F2 1.240 H4/$Net00065-.Fl -

GLOBAL LOGICO 15 PWR-GND - 244.x

1T831 & A 144.F2 1.467 & A 144.F3 2.015 &-A-144.G1 2.006 &-AP142.F2 "

1.831 & A 142.F3

"

"

GLOBAL LOGICO 16 PWR-GND - 26i.x

1,480 & A 48.G1 1.108 &-A-48. " F2

GLOBAL LOGICO 17 PWR-GND 264.x -

2T014 & A 146.F3 2.233 &-A-146.F2 2.503 &-A-148.G1 1.576 &-A-148.F3 2.142 &-A-148.F2 5.448 & A 44.G1 2.680 &-AP44.F2

- _

"


lTl85 & A 83.F2 1.324 & A 75.F2 "

"

GLOBAL LOGICO 19 PWR-GND 29-8.~ -

1,037 H1/$116/$1195.F1

GLOBAL LOGICO-2 PWR-GND - 58.y

11896 S 3 Y < 6 > . F2 1.495 S3Y<4>.G1 1.400 S3Y<4>. F2 2.100 & A 24.F2 2.099 &-A-26.G1 "

1.554 & A 26.F2 "


1,280 & A 162.F3 1.154 & A 164.F3 "

"

GLOBAL LOGICO 21 PWR-GND " 380.x

1.280 & A 158.F3 1.154 & A 160.F3 "

"

GLOBAL LOGICO 3 PWR-Gl:D 6 l. Y

- -

1-319 S3X<2>. F2

GLOBAL LOGICO 4 PWR-GND - ~ O T Y

17416 H8/$113/$1197.F1 1.412 H8/$Net00065-.G4 1.416 H8/SNet00065 .G1 1.416 H8/SNet00065-.Fl -

GLOBAL LOGICO 5 PWR-GND - 9 5 T ~

1,567 S3X<6>. F2 1.428 S3X<4>.G1 l. 447 S3X<4>. F2 1.567 & A 16.F2 1.901 & A 18.G1 1.605 & A 18.F2

"

"

- _

GLOBAL LOGICO 6 PWR-GND " 1 3 0 . ~

1.444 1.313 1.387 1.859 1.700

& A 125.F2 & A 127.G1 & A 127.F2 & A 35.G1 &. A 35.F2

"

"

"

"

"

GLOBAL LOGICO 7 PWR-GND 18i.12 -

3,623 & A 119.G1 4.912 & A 119.F2 5.922 &-A-133.F2 5.780 &-A-135.G1 5.530 &-A-135.F2 "

"

GLOBAL LOGICO 8 & 132.Y "

2.408 & A 100. F2 2.216 &-A-102.G1 1.900 &-A-120. F2 1.941 &-A-120.F1 1.900 H6/$=t00065 .G4 1.440 H6/$Net00065-.F2 1.603 H6/$Net00065-.Fl -

GLOBAL LOGICO 9 PWR-GND - 196.12

3-143 & A 94.G1 "

GLOBAL LOGICl PWR-VCC 77.X -

1,317 S3ZF<O>. G1 1.181 S3ZF<O>.F2

GLOBAL LOGICl O PWR-VCC 1Oo.Y -

1-377 H8/$113/$1197.F2 1.137 H8/$Net00065 .F2 -

GLOBAL LOGICl 1 PWR-VCC 186.Y -

lTOi5 H6/SNetOü065 .G1 -

GLOBAL LOGICl 2 PWR-VCC - 188. X

1,349 & A 94.F2 "

GLOBAL LOGICl 3 PWR-VCC - 225.X

2,825 & A 96.F2 "

GLOBAL LOGICl 4 PWR-VCC 223.Y -

1-035 & A 69.G1 "

GLOBAL LOGICi 5 PWR-VCC 243.Y -

17037 H1/$113/$1195.F1

GLOBAL LOGICl 6 PWR-VCC - 263.X

1T041 & A 46.F2 "

GLOBAL LOGICl 7 PWR-VCC - 322.Y

1T313 & A 156.F3 1.313 & A 154.F3 1.177 H1/$E8/$1195.F1

"

GLOBAL LOGICl 8 PWR-VCC - 356.12

3,265 L A 150.F3 3.265 &A-152.F3 "

Hl/$Il/Cl & A 144.COUT "

0.040 & A 142.CIN "

Hl/$Il/C3 & A 142.COUT "

0.040 Hl/$Net00097 .CIN -

Hl/$Il/C IN Hl/$Ii/$lI95.COUT

0.040 & A 144.CIN "

Hl/$I13/Cl & A 148.COUT "

0.040 & A 146.CIN "

H1/$113/C3 & A 146.COUT "

0.040 Hl/$Net00080 .CIN -

Hl/SI13/C IN H1/$11?/$1195.COUT

0.040 & A 148.CIN "

H1/$116/Cl & A 156.COUT "

0.040 & A 154.CIN "

II1/$;16//C3 & A 154.COUT "

0.040 Hl/$Net00107 .CIN -

Hl/$I16/C IN Hl/$I16/$1195.COUT

0.040 & A 156.CIN "

H1/$118/Cl & A 164.COUT "

0.040 & A 162.CIN "

H1/$118/C3 & A 162.COUT "

0.040 Hl/$Net00127 .CIN -

H1/$118/C IN H1/$118/$1195.COUT

0.040 & A 164 .CIN "

H1/$14/Cl & A 152.COUT "

0.040 & A 150.CIN - _ . H1/$14/C3 & A 15O.COUT "

0.040 Hl/$Net00124 .CIN -

H1/$14/C IN Hl/$I4/$1195.COUT

0.040 & A 152.CIN "

H1/$18/Cl & A 160.COUT "

0.040 & A 158.CIN "

H1/$18/C3 & A 158.COUT "

0.040 Hl/$Net00140 .CIN -

.i1/$18/C IN Hl/$I8/$1195.COUT

0.040 & A 16O.CIN "

Hl/$Net00080 Hl/$Net00580 .X

1.708 -Hl/$I1/$1195.F1

Hl/$Net@0096 & A 142TY "

1.067 & A 140.C2 "

Hl/$Net00097 Hl/$Net00597 .Y

1.019 -& A 140.C1 "

Hl/$Net00107 Hl/SNet@OT07 .x

1.317 -H1/$14/$1195.F1

Hl/$Net00124 Hl/$NetOOi24 .Y

1.037 & A 149.F1 - "

Hl/$Net00127 Hl/$NetOOi27 .x

1.317 -H1/$18/$1195.F1

Hl/$Net00139

Hl/$Net00140 H1/$Net00140 .Y

1.019 -& A 157.F1 "

HlO/$Ill/Cl S3ZF<4>.COUT

0.040 S3ZF<6>.CIN

HlO/$Ill/C3 S3ZF<6>. COUT

0.040 HlO/$Net0@054 .CIN -

HlO/$Ill/C IN H1O/$ILi/$1195.COUT

0.040 S3'ZF<4>.CIN

HlO/$I13/Cl S3ZF<O>.COUT

0.040 S3ZF<2>.CIN

H10/$113/C3 S3ZF<2>.COUT

0.040 HlO/$NetO0127 .CIN -

HlO/$I13/C IN H10/$11~/$1195.COUT

0.040 S3ZF<O>.CIN

HlO/$IlG/Cl S3Y<O>.COUT

0.040 S3Y<2>.CIN

S3Y<2>.COUT 0.040 HlO/$Net00118 .CIN -

HlO/$I16/C IN HlO/$Net00065 .COUT

0.040 53Y<O>.CIN

HlO/SI18/C1 S3X<O>.COUT

0.040 S3X<2>.CIN

H10/$118/C3 S3X<2>.COUT

0.043 KlO;$NetCC053 .C;N -

HlO/$I18/C IN H10/$118/$1195.COUT

0.040 S3X<O>.CIN

HlO/$I3/Cl S3X<4>.COUT

0.040 S3X<6>.CIN

H10/$13/C3 S3X<G>.COUT

0.040 HlO/$Net00104 .CIN -

HlO/$I3/C IN H10/$1?/$1195.COUT

0.040 S3X<4>.CIN

HlO/$I6/Cl S3Y<4>.COUT

0.040 S3Y<G>.CIN

H10/$16/C3 S3Y<G>.COUT

0.040 HlO/$Net00120 .CIN -

HlO/$IG/C IN H10/$16/$1195.COUT

0.040 S3Y<4>.CIN

HlO/$Net00054 HlO/SNet00554 .Y

1.019 23ZF<7>.F1

HlO/$Net00055 S3ZF<6>. Y

-

1.067 S3ZF<7>. F2

HlO/$Net00060 HlO/$Net00~60 .X

2.965 H10/$13/$1195.F1

HlO/$Net00065_ HlO/$Net00065 . X

1.671 S3Y<O>.F3 1.671 S3Y<O>.G3 1.857 S3Y<2>.F3 1.682 S3Y<2>.G1

1.883 4.968 8.860 9.142 8.935 7.846 6.916 6.916

HlO/$Net00118 .F2 H10/$113/$119~.Fl H10/$118/$1195.F1 HlO/$Net00120 .G1 S3Y<6> .G1 S3Y<6>. F3 S3Y<4 >. G3 S3Y<4>. F3

-

HlO/$Net00082 - S3X<6>. Y

1.183 S3X<7>. F3

;::O/S:4etOC:04- HlO/$NetO0104 .Y

2.856 S3X<7>.F2

HlO/$Net00118 HlO/$NetOOi18 .X

4.777 H10/$16/$1195.F1 -

HlO/$Net00119 - S3Y<6>. Y

1.326 S3Y<7>. F1

HlO/$Net00120- HlO/$Net00120 .Y

O. 980 s3Y<7>. F2

HlO/$NetO0127 HlO/$NetOOi27 .X

1.280 ~10/$1ll/$1195.F1

H3/$111/Cl & A 44.COUT "

0.040 & A 42.CIN "

H3/$111/C IN H3/$11i/$lI95..COUT

0.040 & A 44.CIN "

H3/$113/Cl & A 48.COUT "

0.040 & A 46.CIN "

H3/$113/C3 & A 46.COUT "

0.040 H3/$Net00127 .CIN -

H3/$113/C IN H3/$113/$1195.COUT

0.040 & A 48.CIN "

H3/$116/Cl & A 56.COUT "

0.040 & A 54.CIN "

H3/$116/C3 & A 54 .COUT "

0.040 H3/$Net00118-.CIN

H3/$116/C IN H3/$Ner00065 .COUT

0.040 -& A 56.CIN "

H3/SI18/Cl 5 A 64 .COUT - _

0.040 & A G?.CIN "

H3/$118/C3 5 A 62 .CG'JT "

0.040 H3/$Net00060 .CIN -

H3/$118/C IN ii3/$118/$1195.COtiT

0.040 & A 64.CIN "

H3/$13/Cl & A 6O.COUT "

0.040 & A 58.CIN "

H3/$13/C3 & A 58 .corn "

0.040 H3/$Net00104 .CIN -

H3/$13/C IN H3/$13/$1195.COUT

0.040 & A 60.CIN "

H3/$16/Cl & A 52.COUT - _

0.040 & A 50.CIN "

H3/$16/C3 & A 50.COUT "

0.040 H3/$Net00120 .CIN -

H3/$16/C IN H3/$16/$1195.COUT

0 . 0 4 0 & A 52.CIN "

H3/$Net00060 H3/$Net00060 .X

1.260 -H3/$13/$1195.F1

H3/$Net00065 H3/$Net00865 .X

2.504 -& A 56.F3 2.504 & A 56.G3 2.504 & A 54.F3 2.592 & A 54.G1 2.504 H3/$Net00118 .F3

"

"

"

5.426 H3/$113/$1195.F1 1.356 H3/$118/$1195.F1 5.123 H3/$Net00120 .G1 " 4.912 & A 50.G1 5.389 &-A-50. F3 5.38 9 &-A-52 " .G3 5.389 & A 52.F3

-

"

H3/$Net00082 & A 58.Y "

1.868 & A 57.F1 "

H3/$Net00104 H3/$Net00104 .Y

0.980 -& A 5 7 . F 2 "

H3/$Net00118- H3/SNet00118 .X

1.708 -H3/$16/$1195.F1

H3/$Net00119

H3/SNet00120 H3/$NetOOi20 .Y

0.980 -& A 49.F2 "

H3/$Net00127 H3/$Net00127 .x

1.317 -H3/$111/$1195.F1

H4/$111/Cl & A 69.COUT "

0.040 & A 67.CIN "

H4/$111/C IN H4/$Ili/$1195.COUT

0.040 & A 69.CIN --

H4/$113/Cl H4/$Net00065 .COUT

0.040 -& " A 71.CIN

H4/$113/C3

H4/$113/C IN H4/$113/$1195.COUT

0.040 H4/$Net00065 .CIN -

H4/$116/Cl & A 81.COUT "

0.040 & A 79.CIN "

H4/$116/C3 & A 79.COUT "

0.040 H4/$Net00118 .CIN -

H4/$116/C IN & A 6 5 . COUT "

0.040 & A 81.CIN "

H4/$118/Cl & A 89.COUT "

0.040 & A 87.CIN "

H4/$110/C3 & A 87 .COUT "

0.040 H4/$Net00060 .CIN -

I

H4/$118/C IN H4/$118/$1195.COUT

0.040 & A 89.CIN "

H4/$13/C1 & A 85.COUT "

0.040 & A 83.CIN "

H4/$13/C3 & A 83.COUT "

0.040 H4/$Net00104 .CIN -

H?/$I3/C IN H4/$17/$1195.COUT

0.040 & A 85.CIN "

H4/$16/Cl

H4/$16/C3 & A 15.COUT "

0.040 H4/$Net00120 .CIN -

H4/$16/C IN H4/$16/$1195.COUT

0.040 & A 1l.CIN "

H4/$Net00060 H4/$Net00560 .X

4.115 -H4/$13/$1195.F1

H4/$Net00065 H4/$Net00565 .X

1.492 -H4/$113/$1195.F1 3.491 H4/$Net00118 .F3 2.813 3.491 3.491 3.491 1.982

& A 79.G1 & A 79.F3 & A 81.G3 & A 81.F3 H4/$Gt00120 . G 1

-

"

"

"

1.982 & A 15.G1 3.491 &A-75.F3 3.491 &-A-ll.G3 3.491 & A 17.F3

-

"

H4/$Net00082 & A 83.Y "

1.256 & A 82.F2 "

H4/$Net00104 H4/$NetOOi04 .Y

1.019 & A 82. F1 - "

H4/$Net00118 H4/$Net00118-.X

1.316 H4/$16/$1195.F1

H4/$Net00119 & A 15.Y "

1.614 & A. 74.F2 "

H4/$Net00120 H4/$Net00120 - .Y

1.037 & A 74.F1 "

H4/SNet00127 H4/$Net00127 .x

1.317 H4/$111/$1195.F1 -

H5/$111/Cl & A 94 .COUT "

0.040 & A 92.CIN "

H5/$111/C IN H5/$11T/$1195.COUT

0.040 & A 94.CIN "

H5/$113/Cl H5/$Net00065 .COUT

0.040 -& A 96.CIN "

H5/$113/C3 & A 96.COUT "

0.040 H5/$Net00127 .CIN -

H5 'SI13/C IN .i5/$113/$1195.COUT

0.040 H5/$Net00065 .CIN -

H5/$116/Cl & A 106.COUT "

0.040 & A 104.CIN "

H5/$116/C3 & A 104.COUT "

0.040 H5/$Net00118 .CIN -

H5/$116/C IN H5/$116/$1195.COUT

0.040 & A 106.CIN "

H5/$118/Cl & A 114.COUT "

0.040 & A 112.CIN "

H5/$118/C3 & A 112.COUT "

0.040 H5/$Net00060 .CIN -

H5/$118/C IN H5/$118/$1195.COUT

0.040 & A 114.CIN "

H5/$13/Cl & A 11O.COUT "

0.040 & A 108.CIN "

H5/$13/C3 & A 108.COUT "

0.040 H5/$Net00104 - .CIN

H5/$13/C IN HS/$I3/$1195.COUT

0.040 & A 11O.CIN "

H5/$16/Cl & A 102.COUT "

0.040 & A 1OO.CI:. "

H5/$16/C3

ii5/$IG/C Iiu' H5/$16/$1195.COUT

0.040 & A 102.CIN "

H5/$Net00060 H5/$Net00860 .X

2.471 -H5/$13/$1195.F1

H5/$Net00065 H5/$Net00865 .X

2.021 -H5/$113/$1195.F1 9.244 H5/$Net00118 .F3 3.590 & A 104.G1- 9.455 &A-104.F3 9.570 &-A-106.G3 9.570 &-A-106.F3 3.053 H5/$E8/$1195.F1 2.110 H5/SNet00120 .G1 1.950 & A 100.G1- 2.791 &-A-100.F3 2.791 & A 102.G3 2.791 &-A-102.F3

"

"

H5/$Net00082 & A 108TY "

1.183 & A 107.F3 "

H5/$Net00104 H5/$Net00¡04 .Y

2.853 -& A 107.F4 "

H5/$Net00118 HS/$NetOOi18 .X

5.230

H5/$Net00119 &-A - l00,Y

1.067

- H5/$16/$1195.F1

~~

& A 99. F2 "

H5/$Net00120 H5/$NetOOi20 .Y

1.019 -& A 99.F1 "

H5/$Net00127 H5/$NetOOi27 .x

1.317 -H5/$111/$1195.F1

& A 119.COUT "

0.040 & A 117.CIN "

H6/$Ill/C IN H6/$11T/$1195.COUT

0.040 & A 119.CIN "

H6/$113/Cl H6/$Net00065 .COUT

0.040 -& A i20.CIN "

H6/$113/C3 & A 12O.COUT "

0.040 H6/SNet00127 .CIN -

H6/$113/C IN H6/$113/$1195.COUT

0.040 H6/$Net00065 .CIN -

H6/$116/Cl & A 131.COUT "

0.040 & A 129.CIN "

H6/$116/C3 & A 129.COUT "

0.040 H6/$Net00118 .CIN -

H6/$116/C IN & A I~~.COUT "

0.040 & A 131.CIN "

H6/$118/Cl & A 139.COUT "

0.040 & A 137.CIN "

H6/$118/C3 & A 137.COUT "

0.040 H6/$Net00060 .CIN -

H6/$118/C IN H6/$118/$1195.COUT

0.040 & A 139.CIN "

H6/$13/Cl & A 135.COUT "

0.040 & A 133.CIN "

H6/$13/C3 & A 133.COUT "

0.040 H6/$Net00104 .CIN -

H6/$13/C IN H6/$1~/$1195.COUT

0.040 & A 135.CIN "

H6/$16/C1 & A 127.COUT "

0.040 & A 125.CIN "

H6/$16/C3 & A 125.COUT "

0.040 H6/$Net00120 .CIN -

H6/$16/C IN H6/$16/$1195. COUT

0.040 & A 127.CIN "

H6/$Net00060 H6/$Net00560 .X

2.211 -H6/$13/$1195.F1

H6/$Net00065 H6/$Net00065 .X

1.591 -H6/$113/$1195.F1 1 . S76 85/$MetCl0118 . F3 5.335 & A 129.G1- 1.976 &-A-129.F3 2.169 &-A-131.G3 2.169 &-A-131.F3 2.506 H6/$58/$1195.F1 6.693 H6/$Net00120 .G1 6.541 & A 125.G1- 2.352 &-Ae125.F3 2.352 &A-127.G3 "

2.352 & A 127.F3 "

H6/$Net00082 & A 133TY "

1.614 & A 132.F2 "

H6/$Net00104- H6/$Net00104 .Y

1.037 & A 132.F1 - "

H6/$Net00118- H6/$Net00118 .X

2.800 -H6/$16/$1195.F1

H6/$Net00119- & A 125.Y "

1.319 & A 124.F2 "

H6/$Net0012b H6/$Net00720 - .Y

1.037 & A 124.F1 "

H6/$Net00127 H6/$Net00727 .X

1.426 -H6/$111/$1195.F1

H8/$111/Cl & A 35.COUT "

0.040 & A 33.CIN "

H8/$111/C IN H8/$1li/$lI95.COUT

0.040 & A 35.CIN "

H8/$113/Cl H8/$Net00065 .COUT

0.040 -H8/$113/$1197.CIN

H8/$113/C3 H8/$113/$1197.COUT

0.040 H8/$Net00127 .CIN -

H8/$113/C IN H8/$113/$1195.COUT

0.040 H8/$Net00065 .CIN -

H8/$116/Cl & A 30.COUT "

0.040 & A 28.CIN "

H8/$116/C3 & A 28.COUT "

0.040 H8/$Net00118 .CIN -

Htii$Ii6/C IN H8/$116/$1195.COUT

0.040 & A 30.CIN "

H8/$118/Cl & A 22.COUT "

0.040 & A 20.CIN "

H8/$118/C3 & A 20.COUT "

0.040 H8/$Net00060 .CIN -

H8/$118/C IN H8/$118/$1195.COUT

0.040 & A 22.CIN "

H8/$13/Cl & A 18 .COUT "

0.040 & A 16.CIN "

H8/$13/C3 & A 16.COUT - _

0.040 H8/$Net00104 .CIN -

H8/$13/C IN H8/$13/$1195.COUT

0.040 & A 18.CIN "

H8/$16/C1 & A 26.COUT "

0.040 & A 24.CIN "

H8/$16/C3 & A 24 .COUT "

0.040 H8/$Net00120 .CIN -

H8/$16/C IN H8/$16/$1195.COUT

0.040 & A 26.CIN "

H8/$Net00060 H8/$Net00560 .X -

2.114 H8/$13/$1195.F1

H8/$Net00065 .X 1.056 -H8/$113/$1195. F1 10.741 H8/$Net00118 .F2 9.697 & A 28 .GI 9.833 &-A-28.F3 9.833 &-A-30.G3

-

9.833 & A 30.F3 4.464 H8/$=8/$1195.F1

"

5.694 H8/$Net00120 .G1 5.879 & A 24.G1 4.033 & A 24.F3 2.641 & A 26.G3 2.641 &-A-26.F3 - _

- "

"

H8/$Net00104 H8/$Net00104 .Y

0.980 & A 15.F2 - "

H8/$Net00118 H8/$Net00118 .X

3.512 -H8/$16/$1195.F1

H8/$Net00119- & A 24.Y "

1.067 & A 23.F2 "

H8/$Net00120- H8/$Net00120 .Y

1.019 & A 23.F1 - "

H8/$Net00127 H8/$NetOOi27 .X

1.317 -H8/$111/$1195.F1

S3X<O> s3x<o>. x

2.855 $Net00008 - .O

S3X<1> s3x<o>. Y

2.300 $Net00001 - .O

S3X<2> s3x<2>. x

3.838 $Net00002 - .O

s3x<3> s3x<2>. Y

2.199 $Net00003 - .O

s3x<4> s3x<4>. x

2.468 $Net00004 - .O

s3x<5> S3X<4>.Y

2.940 $Net00005 - .O

S3X<6> S 3 x < 6 > . x

2 . 2 2 1 $ N e t 0 0 0 0 6 - . O

s 3 x < 7 > s 3 x < 7 > . x

2 . 1 1 2 $ N e t 0 0 0 0 7 - . O

S3Y<O> s3Y<o> . x

2 . 2 3 3 $ N e t 0 0 0 1 7 -

S3Y<1> s3Y<o>. Y

2 . 1 0 9 $ N e t 0 0 0 1 8

S3Y<2> s3Y<2>. x

5 . 6 8 9

S3Y<3> s3Y<2>. Y

8 . 8 1 8

S3Y<4> S3Y<4>.X

1 . 7 0 3

S3Y<5> S3Y<4>.Y

3 . 9 9 2

S3Y<6> S3Y<6>. x

1 . 7 0 3

S3Y<7> S3Y<7>. x

2 * 555

S3ZF<O> S3ZF<O>. X

1 . 3 1 3

S3ZF<1> S3ZF<O>. Y

2 . 2 0 9

S3ZF<2> S3ZF<2> . X

1.696

S3ZF<3> S3ZF<2>. Y

2 . 1 4 2

S3ZF<4> S3ZF<4>.X

l. 313

. o

.e

$ N e t 0 0 0 1 9 - .O

$Net00020 - . O

$ N e t 0 0 0 2 1 - . O

$ N e t 0 0 0 2 2 - . O

$ N e t 0 0 0 2 3 - . O

$Ne t00024 - . O

$ N e t 0 0 0 0 9 - . O

$Ne t00010 - . O

$ N e t 0 0 0 1 1 - . O

$ N e t 0 0 0 1 2 - . O

$ N e t 0 0 0 1 3 - . O

S3ZF<5> S3ZF<4>.Y

2.470 $Net00014 - .O

S3ZF<6> S3ZF<6>.X

1.313 $Net00015 - .O

S3ZF<7> S3ZF<7> . X

2.555 SNet00016..0 -

Trazo

Retardo máximo de pistas combinacionales 150.48111s Retardo máximo de red 12.17511s.

El circuito tiene 98785707 pistas, 395 redes y 65 1 conexiones.

En un FPGA típico, la suma de los retardos del trazado a lo largo de las pistas criticas, comprende la mitad del retardo total. En un diseño el retardo del trazo es la estimación más importante. El retardo debido a una interconexión particular, depende de la capacitancia y la resistencia de la interconexión, las cuales dependen de la colocación fisica de las conexiones. Esto también depende de la arquitectura del encaminamiento, para el dispositivo, así como de su tamaiio. Una buena estimación de los retardos del trazado, depende de una buena estimación de la colocación fisica y de un conocimiento detallado de la arquitectura del dispositivo.

Las opciones que existen para la optimización del tiempo son:

Cambiar la topología del circuito en las pistas criticas, de tal manera que tengan menores retardos.

Cambiar la disposición de manera que sea más fácil hacer rutas con menos resistencia y capacitancia.

Cambiar el encaminamiento para reducir resistencia y capacitancia.

La velocidad del &seiio de un FPGA depende de muchos factores, a continuación se mencionan algunos de ellos:

El retardo en la más simple celda lógica programable.

El retardo introducido por el encaminamiento.

La interconexión lógica para formar una pista crítica en el circuito.

Los requerimientos de tiempo de la circuiteria externa.

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""""

Xilinx TRACE, Version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved.

Design file: emma. ncd Physical constraint file: emma.pcf Device, speed: xCs30,-3 (x1 0.14 1.6 PRELIMINARY) Report level: error report, limited to 3 items per constraint .....................................

WARNING:bastw:170 - No timing constraints found, doing default enumeration.

....................................

....................................

"" "" " -" - - - Timing constraint: Default period analysis 98785707 items analyzed, O timing errors detected. Maximum delay is 150.481ns. .....................................

......................................

....................................

"""" """"

Timing constraint: Default net enumeration 395 items analyzed, O timing errors detected. Maximum net delay is 12.175ns. .......................................

""""

All constraints were met

Timing summary: """""""_ Timing errors: O Score: O

Design statistics: Maximum combinational path delay: 150.481ns Maximum net delay: 12.175ns

Analysis completed Sun Mar 26 15:46:22 2000 "~""~"""_""""""""""""""""""""""""""""- - - - - - - - -

Loading device database for application Bitgen from file "emma.ncd".

Loading device for application Bitgen from file '4013e.nph' in environment C: /fndtn. Opened constraints file emma.pcf.

'lemma" is an NCD, version 2.27, device xcs30, package vq100, speed -3

BITGEN: Xilinx Bitstream Generator M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved

Sun Mar 26 15:46:28 2000

bitgen -1 -w -g ConfigRate:SLOW -g TdoPin:PULLNONE -g DonePin:PULLUP -g CRC:enable -g StartUpC1k:CCLK - g SyncToDone:no -9 DoneActive:Cl -g OutputsActive:C3 -g GSRInactive:C4 -g ReadC1k:CCLK -4 ReadCapture:enable -g ReadAb0rt:disable emma.ncd

Running DRC. DRC detected O errors and O warnings. Saving 11 file in 'lemma. 11". Creating bit map . . . Saving bit stream in "emma. bit".

CONCLUSIONES

El análisis de voz ha tenido un impacto significativo en las comunicaciones, ya que el desarrollo de las técnicas de compresión, para diferentes propósitos como pueden ser el almacenamiento o la transmisión de la voz, ha permitido el incremento de aplicaciones, como es el caso de las comunicaciones inalámbricas, telefonía digital, etc.

A partir del desarrollo que aquí se ha propuesto, se puede observar que el análisis de voz puede realizarse en hardware usando el algoritmo CORDIC para obtener las seaales seno y coseno de una manera sencilla, que además necesita de pocos recursos en cuanto a circuiteria se refiere, como ya se ha mencionado con este método es innecesario el uso de memorias o multiplicadores, lo que reduce complejidad y costo en el diseño.

Este proyecto se realizó dentro de un circuito integrado FPGA (Field Programmable Gate Array). El diseiio en un circuito integrado de este tipo, ha permitido un desarrollo de forma accesible; esta técnica permite la disposición y el trazado de los elementos de manera automática, por lo tanto se requiere poco tiempo para el diseño, aunque también puede configurarse manualmente cuando el tiempo no está limitado, y las características así lo requieran. Además es una herramienta muy potente para el desarrollo de prototipos, pues se pueden hacer los cambios que sean necesarios para el resultado óptimo del circuito, sin que esto represente una tarea extremadamente dficil.

Finalmente resta mencionar que el circuito integrado se diseñó en un principio para ser descargado dentro de un dispositivo XS30, pero en el diagrama interno se observó que el espacio podría optimizarse utilizando un XS10, ya que este tiene una superficie menor y esto da como resultado el uso eficiente de los recursos.

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REFERENCIAS

Digital Signal Processing in Communication Systems. Marvin E. Frerking. Chapman & Hall. 1994.

Digital Communications 1.A.Glover P.M.Grant. Prentice Hall. 1998.

Information Transmission, Modulation and Noise. Mischa Schwartz. Mc.Graw Hill. 1990.

htto://rice.ecs,soton.ac.uk/iason/speech codecd Mobile Multimedia Research at the university of Southampton.

http://www.math.utep.edu/Facult~/helmut/cordic/wcordic.html Charles W.Schelin. Calculator Functions Approximation. American Math. 1983.

http://users.ids.net/-randrakdcordic. htm Andraka consulting group. inc A survey of cordic algorithms for FPGA’s.

ftu:~/ttD.cs.indiana.edu/pub/aoo/RobNav/scordic.c The swiss army knife for computing math functions ...

Implementing cordic algorithms. Jarvis.P. 1990.

DSP Spring Design Conference. Speech and Audio Coding Algorithms: An Overview of Standards and Applications. Cole Erskin. April. 1999.

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